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ADS7882IPFBT Datasheet(PDF) 8 Page - Texas Instruments |
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ADS7882IPFBT Datasheet(HTML) 8 Page - Texas Instruments |
8 / 29 page DESCRIPTION AND TIMING DIAGRAMS SAMPLING AND CONVERSION START th2 th3 td1 td2 t(acq) CS CONVST BUSY td3 t(acq) tw3 tw3 td4 tw1 CS CONVST BUSY t(acq) tw4 td2 CS CONVST BUSY th1 tw5 ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com There are three ways to start sampling. The rising edge of CONVST starts sampling with CS and BUSY being low (see Figure 1) or it can be started with the falling edge of CS when CONVST is high and BUSY is low (see Figure 2). Sampling can also be started with an internal conversion end (before BUSY falling edge) with CS being low and CONVST high before an internal conversion end (see Figure 3). Also refer to the section DEVICE OPERATION AND DATA READ IN BACK-TO-BACK CONVERSION for more details. A conversion can be started two ways (a conversion start is the end of sampling). Either with the falling edge of CONVST when CS is low (see Figure 1) or the falling edge of CS when CONVST is low (see Figure 2). A clean and low jitter falling edge of these respective signals triggers a conversion start and is important to the performance of the converter. The BUSY pin is brought high immediately following the CONVST falling edge. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Figure 1. Sampling and Conversion Start Control With CONVST Pin Figure 2. Sampling and Conversion Start Control With CS Pin Figure 3. Sampling Start With CS Low and CONVST High (Back-to-Back) 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 |
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