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TPS73701DRBTG4 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS73701DRBTG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 22 page PIN CONFIGURATIONS IN N/C N/C EN 8 7 6 5 OUT N/C NR/FB GND 1 2 3 4 DRBPACKAGE 3mmx3mmSON (TOPVIEW) DCQPACKAGE SOT223 (TOPVIEW) 1 2 3 4 5 IN OUT GND NR/FB EN TABISGND 6 TPS737xx www.ti.com ....................................................................................................................................................... SBVS067H – JANUARY 2006 – REVISED MAY 2008 Table 1. Pin Descriptions SOT223 3 ×3 SON PIN (DCQ) (DRB) NAME PIN NO. PIN NO. DESCRIPTION IN 1 8 Unregulated input supply GND 3, 6 4, Pad Ground Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into EN 5 5 shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN must not be left floating and can be connected to IN if not used. Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated NR 4 3 by the internal bandgap, reducing output noise to very low levels. Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set FB 4 3 the output voltage of the device. OUT 2 1 Regulator output. A 1.0 µF or larger capacitor of any type is required for stability. NC — 2, 6, 7 Not connected Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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