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TSC2008IRGVR Datasheet(PDF) 6 Page - Texas Instruments |
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TSC2008IRGVR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 37 page TIMING INFORMATION BIT0 t DIS(CSR-SDOZ) t H(SDI-SCLKR) NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequires8SCLKs. t H(SCLKF-SDOVALID) t SU(SDI-SCLKR) t D(CSF-SDOVALID) t SU(SCLKF-CSR) t WH(CS) t C(SCLK) t SU(CSF-SCLK1R) t F t R t WL(SCLK) t WH(SCLK) BIT1 MSBIN MSBOUT CS SS ( ) SCLK SDO(MISO) SDI(MOSI) BIT0 BIT1 CS SCLK PENIRQ/BUSY (TSC2008) t D(SCLKR-PENIRQF) t SU(PENIRQR-SCLKR) t D(SCLKF-PENIRQF) TSC2008 SBAS406A – JUNE 2008 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com The TSC2008 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to change the output (MISO) data, and the rising edge is used to latch the input (MOSI) data. Eight SCLKs are required to complete the command byte cycle, and an additional eight or 16 SCLKs are required for the data to be read, depending on the mode used. Figure 1. Detailed I/O Timing Figure 2. PENIRQ Timing 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2008 |
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