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CS2000-CP-CZZR Datasheet(PDF) 8 Page - Cirrus Logic

No. de Pieza. CS2000-CP-CZZR
Descripción  Fractional-N Clock Synthesizer & Clock Multiplier
Descarga  36 Pages
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Fabricante  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
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CS2000-CP-CZZR Datasheet(HTML) 8 Page - Cirrus Logic

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CS2000-CP
8
DS761PP1
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Grade);
CL =15pF.
Notes: 3.
1 UI (unit interval) corresponds to tSYS_CLK or 1/fSYS_CLK.
4.
tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of tCS.
5.
Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 14 for more information.
6.
fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
7.
In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8.
In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9.
1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
Parameters
Symbol
Conditions
Min
Typ
Max
Units
Crystal Frequency
fXTAL
Fundamental Mode
8
-
50
MHz
Reference Clock Input Frequency
fREF_CLK
8-
75
MHz
Reference Clock Input Duty Cycle
DREF_CLK
45
-
55
%
Internal System Clock Frequency
fSYS_CLK
8
18.75
MHz
Clock Input Frequency (Auto R-Mod Disabled)
fCLK_IN
50 Hz
-
30
MHz
Clock Input Frequency (Auto R-mod Enabled)
fCLK_IN
Auto R Modifier = 1
Auto R Modifier = 0.5
Auto R Modifier = 0.25
4
72
168
-
-
-
59
138
256
kHz
kHz
kHz
Clock Input Pulse Width (Note 3)pwCLK_IN
fCLK_IN < fSYS_CLK/96
fCLK_IN > fSYS_CLK/96
2
10
-
-
-
-
UI
ns
Clock Skipping Timeout
tCS
(Notes 4, 5)20
-
-
ms
Clock Skipping Input Frequency
fCLK_SKIP
(Note 5)
50 Hz
-
80
kHz
PLL Clock Output Frequency
fCLK_OUT
6-
75
MHz
PLL Clock Output Duty Cycle
tOD
Measured at VD/2
48
50
52
%
Clock Output Rise Time
tOR
20% to 80% of VD
-
1.7
3.0
ns
Clock Output Fall Time
tOF
80% to 20% of VD
-
1.7
3.0
ns
Period Jitter
tJIT
(Note 6)
-
70
150
ps rms
Base Band Jitter (100 Hz to 40 kHz)
(Notes 6, 7)
-
50
-
ps rms
Wide Band JItter (100 Hz Corner)
(Notes 6, 8)
-
175
-
ps rms
PLL Lock Time - CLK_IN (Note 9)tLC
fCLK_IN < 200 kHz
fCLK_IN > 200 kHz
-
-
100
1
200
3
UI
ms
PLL Lock Time - REF_CLK
tLR
fREF_CLK = 8 to 75 MHz
-
1
2
ms
Output Frequency Synthesis Resolution (Note 10)ferr
High Resolution
High Multiplication
0
0
-
-
±0.5
±112
ppm
ppm


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