CS2000-CP

24

DS761PP1

6. SPI / I²C CONTROL PORT

The control port is used to access the registers and allows the device to be configured for the desired operational

modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs

and outputs. However, to avoid potential interference problems, the control port pins should remain static if no op-

eration is required.

The control port operates with either the SPI or I²C interface, with the CS2000 acting as a slave device. SPI Mode

is selected if there is a high-to-low transition on the AD0/CS pin after power-up. I²C Mode is selected by connecting

the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state.

In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation.

WARNING: All “Reserved” registers must maintain their default state to ensure proper functional operation.

6.1

SPI Control

In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller),

and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The

device only supports write operations.

Figure 17 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first

eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Ad-

dress Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are

the data which will be placed into the register designated by the MAP.

There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the

MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically incre-

ment after each byte is read or written, allowing block writes of successive registers.

6.2

I²C Control

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL.

There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected

to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the

device.

The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is de-

fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the

a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The

upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The

Referenced Control

Register Location

EnDevCfg1 ............................“Enable Device Configuration Registers 1 (EnDevCfg1)” on page 29

EnDevCfg2 ............................“Enable Device Configuration Registers 2 (EnDevCfg2)” section on page 30

4

5

6

7

CCLK

CHIP ADDRESS

MAP BYTE

DATA

1

0

0

1

1

1

1

0

CDIN

INCR

6

5

4

3

2

1

0

7

6

1

0

0

1

2

3

8

9

12

16 17

10 11

13 14 15

DATA +n

CS

7

6

1

0

Figure 17. Control Port Timing in SPI Mode