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CDB4365 Datasheet(PDF) 15 Page - Cirrus Logic |
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CDB4365 Datasheet(HTML) 15 Page - Cirrus Logic |
15 / 52 page DS670F2 15 CS4365 SWITCHING CHARACTERISTICS - PCM Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF. Notes: 14. After powering up, RST should be held low until after the power supplies and clocks are settled. 15. See Tables 1 - 3 for suggested MCLK frequencies. 16. MSB of CH1 is always the second SCLK rising edge following LRCK rising edge. Parameters Symbol Min Max Units RST pin Low Pulse Width (Note 14) 1- ms MCLK Frequency 1.024 55.2 MHz MCLK Duty Cycle (Note 15) 45 55 % Input Sample Rate - LRCK (Manual selection) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 4 50 100 54 108 216 kHz kHz kHz Input Sample Rate - LRCK (Auto detect) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 4 84 170 54 108 216 kHz kHz kHz LRCK Duty Cycle 45 55 % SCLK Duty Cycle 45 55 % SCLK High Time tsckh 8- ns SCLK Low Time tsckl 8- ns LRCK Edge to SCLK Rising Edge tlcks 5- ns SCLK Rising Edge to LRCK Falling Edge tlckd 5- ns SDIN Setup Time Before SCLK Rising Edge tds 3- ns SDIN Hold Time After SCLK Rising Edge tdh 5- ns SDINx t ds SCLK LRCK MSB t dh t sckh t sckl t lcks MSB-1 Figure 1. Serial Audio Interface Timing |
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