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ML2726DH-T Datasheet(PDF) 6 Page - SIRENZA MICRODEVICES |
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ML2726DH-T Datasheet(HTML) 6 Page - SIRENZA MICRODEVICES |
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6 / 25 page  ML2726 PRELIMINARY DATASHEET OCT 2007 EDS-105982 REV P01 6 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRSMD RSSI midrange voltage -40dBm into RXI 1.4 1.7 2.0 V VRSMN RSSI minimum voltage No signal into RXI 75 mV VRSMXC RSSI maximum voltage (clipped) -10dBm into RXI 1.6 1.95 V TRANSMIT RF MIXER POSE Output power, single ended TRXO or TRXOB, fC=2.445GHz -3 1 5 dBm PODIF Output power, differential P(TRXO,TRXOB), fC=2.445GHz -1 3 6 dBm ZOUT Output impedance TRXO or TRXOB, fC=2.445GHz 12+j0 Ω TRANSMIT MODULATION fDEV Modulation Deviation, @2.4GHz 200us of consecutive ‘1’s or ‘0’s 750 768 786 kHz fOS Modulation center frequency offset 50us after RXON low -75 +75 kHz TRANSMIT DATA FILTER BWTX Transmit Data Filter Bandwidth 3dB Bandwidth 2.1 MHz TX spurious Image -25 -20 dBc dBc INTERFACE LOGIC LEVELS INPUTS (DIN, XCEN, RXON, DATA, CLK, EN) VIH Input high voltage (never exceed VDD) 0.75*VDD VDD V VIL Input low voltage 0 0.25*VDD V IB Input bias current -5 0 5 μA CIN Input capacitance (measured at 1MHz) 4 pF OUTPUTS (DOUT, PAON) VOH DOUT high voltage Io=0.1mA VDD-0.4 V VOL DOUT low voltage Io=-0.1mA 0.4 V Io DOUT sink/source current 0.1 mA VOH PAON output high voltage Sourcing 0.5mA VDD-0.4 V VOL PAON output low voltage Sinking 0.5mA 0.4 V Io PAON source/sink current 0.5 mA 3 WIRE SERIAL BUS TIMING tr CLK input rise time 15 ns tf CLK input fall time 15 ns tck CLK period 50 ns tew CLK pulse width 100 ns tl Delay from last CLK falling edge 15 ns tse EN setup time to ignore next rising CLK 15 ns ts DATA-to-CLK setup time 15 ns th DATA-to-CLK hold time See Figure 4 15 ns |
Número de pieza similar - ML2726DH-T |
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Descripción similar - ML2726DH-T |
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