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T89C5115 Datasheet(PDF) 85 Page - ATMEL Corporation |
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T89C5115 Datasheet(HTML) 85 Page - ATMEL Corporation |
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85 / 113 page  85 AT89C5115 4128G–8051–02/08 The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 60. Selected Analog input Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range (See section “AC-DC”). Clock Selection The ADC clock is the same as CPU. The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres- caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. if PRS = 0 then FADC = Fperiph / 64 if PRS > 0 then FADC = Fperiph / 2 x PRS Figure 40. A/D Converter Clock ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is reduced. IT ADC management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. SCH2 SCH1 SCH0 Selected Analog Input 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 Prescaler ADCLK A/D Converter ADC Clock CPU CLOCK CPU Core Clock Symbol ÷ 2 |
Número de pieza similar - T89C5115_08 |
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Descripción similar - T89C5115_08 |
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