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CDCE62005 Datasheet(PDF) 1 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 76 page 1 FEATURES APPLICATIONS CDCE62005 www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008 Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs • Frequency Synthesizer With PLL/VCO and • Flexible Inputs With Innovative Smart Partially Integrated Loop Filter. Multiplexer Feature: • Fully Configurable Outputs Including – Two Universal Differential Inputs Accept Frequency, Output Format, and Output Skew. Frequencies up to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS). • Smart Input Multiplexer Automatically Switches Between One of Three Reference – One Auxiliary Input Accepts Single Ended Inputs. Clock Source or Crystal. Auxiliary Input Accepts Crystals in the Range of 2 MHz–42 • Multiple Operational Modes Include Clock MHz or an LVCMOS Input up to 75 MHz. Generation via Crystal, SERDES Startup Mode, Jitter Cleaning, and Oscillator Holdover Mode – Clock Generator Mode Using Crystal Input. • Integrated EEPROM Determines Device – Smart Input Multiplexer can be Configured Configuration at Power-up to Automatically Switch Between Highest Priority Clock Source Available Allowing • Excellent Jitter Performance for Fail-safe Operation and Holdover • Integrated Frequency Synthesizer including Modes. PLL, Multiple VCOs, and Loop Filter: • Typical Power Consumption 1.7W – Full Programmability Facilitates Phase (See Table 44) at 3.3V Noise Performance Optimization Enabling • Integrated EEPROM Stores Default Settings; Jitter Cleaner Mode. Therefore, The Device Can Power up in a – Programmable Charge Pump Gain and Known, Predefined State. Loop Filter Settings • Offered in QFN-48 Package – Unique Dual-VCO Architecture Supports a • ESD Protection Exceeds 2kV HBM Wide Tuning Range 1.750 GHz–2.356 GHz • Industrial Temperature Range –40°C to 85°C • Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or Combinations of Differential or Single-ended: • Data Converter and Data Aggregation Clocking – 1 ps RMS (10 kHz to 20 MHz) Output Jitter • Wireless Infrastructure Performance • Switches and Routers – Low Output Phase Noise: –130 dBc/Hz at 1 • Medical Electronics MHz offset, Fc = 491.52 MHz • Military and Aerospace – Output Frequency Ranges from 4.25 MHz to • Industrial 1.175 GHz in Synthesizer Mode • Clock Generation and Jitter Cleaning – Output Frequency up to 1.5 GHz in Fan-out Mode – LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes – Independent Output Dividers Support Divide Ratios from 1–80(1) – Independent Coarse Skew Control on all Outputs (1) Non-continuous values supported. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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