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SMJ320CC6713BGDPS20EP Datasheet(PDF) 5 Page - Texas Instruments

No. de Pieza. SMJ320CC6713BGDPS20EP
Descripción  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Descarga  123 Pages
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Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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SMJ320CC6713BGDPS20EP Datasheet(HTML) 5 Page - Texas Instruments

 
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FEATURES
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SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
SM320C6713-EP
SM320C6713B-EP
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
www.ti.com
SGUS049H – AUGUST 2003 – REVISED SEPTEMBER 2008
• 32 Bit External Memory Interface (EMIF)
• Highest Performance Floating Point Digital
Signal Processors (DSPs): C6713/C6713B
Glueless Interface to SRAM, EPROM, Flash,
SBSRAM, and SDRAM
Eight 32 Bit Instructions/Cycle
512M Byte Total Addressable External
32/64 Bit Data Word
Memory Space
200 and 300 MHz Clock Rate
• Enhanced Direct Memory Access (EDMA)
5 Instruction Cycle Times
Controller (16 Independent Channels)
2400/1800 and 1600/1200 MIPS/MFLOPS
• 16 Bit Host Port Interface (HPI)
Rich Peripheral Set, Optimized for Audio
Highly Optimized C/C++ Compiler
• Two Multichannel Audio Serial Ports (McASPs)
Two Independent Clock Zones Each
• Advanced Very Long Instruction Word (VLIW)
(One TX and One RX)
320C67x™ DSP Core
Eight Serial Data Pins Per Port: Individually
Eight Independent Functional Units:
Assignable to any of the Clock Zones
• Two ALUs (Fixed Point)
Wide Variety of I2S™ and Similar Bit Stream
• Four ALUs (Floating Point and Fixed
Formats
Point)
Integrated Digital Audio Interface
• Two Multipliers (Floating Point and
Transmitter (DIT)
Fixed Point)
Extensive Error Checking and Recovery
Load Store Architecture With 32 32-Bit
• Two Inter-Integrated Circuit Bus (I2C™ Bus)
General Purpose Registers
Multi-Master and Slave Interfaces
Instruction Packing Reduces Code Size
All Instructions Conditional
• Two Multichannel Buffered Serial Ports:
Serial Peripheral Interface (SPI)
• Instruction Set Features
High Speed TDM Interface
Native Instructions for IEEE 754
AC97 Interface
Byte Addressable (8/16/32 Bit Data)
8 Bit Overflow Protection
• Two 32 Bit General Purpose Timers
Saturation; Bit-Field Extract, Set, Clear;
• Dedicated GPIO Module With 16 Pins (External
Bit-Counting; Normalization
Interrupt Capable)
• L1/L2 Memory Architecture
• Flexible Phase Locked Loop (PLL) Based
4K Byte L1P Program Cache
Clock Generator Module
(Direct-Mapped)
• IEEE-1149.1 (JTAG)(1) Boundary-Scan
4K Byte L1D Data Cache (2-Way)
Compatible
256K Byte L2 Memory Total: 64K-Byte L2
• 272 Ball, Ball Grid Array Package (GDP)
Unified Cache/Mapped RAM, and 192K Byte
• 0.13 µm/6 Level Copper Metal Process
Additional L2 Mapped RAM
CMOS Technology
• Device Configuration
• 3.3 V I/Os, 1.26 V Internal
Boot Mode: HPI, 8/16/32 Bit ROM Boot
(1)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Endianness: Little Endian, Big Endian
Boundary Scan Architecture.
break
• Controlled Baseline
• Extended Product Life Cycle
• One Assembly/Test Site
• Extended Product-Change Notification
• One Fabrication Site
• Product Traceability
• Available in Military (–55°C/125°C)
Temperature Range(2)
(2)
Custom temperature ranges available
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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