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SMJ320CC6713BGDPS20EP Datasheet(PDF) 87 Page - Texas Instruments |
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SMJ320CC6713BGDPS20EP Datasheet(HTML) 87 Page - Texas Instruments |
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87 / 123 page  11.5 Input and Output Clocks CLKIN 1 2 3 4 4 CLKOUT2 1 2 3 4 4 SM320C6713-EP SM320C6713B-EP FLOATING-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS049H – AUGUST 2003 – REVISED SEPTEMBER 2008 Table 11-2. Timing Requirements for CLKIN(1)(2)(3) See Figure 11-5 PLL MODE BYPASS MODE (PLLEN = 1) (PLLEN = 0) NO. UNIT MIN MAX MIN MAX tc(CLKI GDP-200 5 83.3 6.7 1 Cycle time, CLKIN ns N) GDP-300 4 83.3 6.7 tw(CLKI 2 Pulse duration, CLKIN high 0.4C 0.4C ns NH) tw(CLKI 3 Pulse duration, CLKIN low 0.4C 0.4C ns NL) tt(CLKIN 4 Transition time, CLKIN 5 5 ns ) (1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (2) C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. (3) See the PLL and PLL Controller section of this data sheet. Figure 11-5. CLKIN Table 11-3. Switching Characteristics for CLKOUT2(1)(2) over recommended operating conditions (see Figure 11-6) NO. PARAMETER MIN MAX UNIT 1 tc(CKO2) Cycle time, CLKOUT2 C2 – 0.8 C2 + 0.8 ns 2 tw(CKO2H) Pulse duration, CLKOUT2 high (C2/2) – 0.8 (C2/2) + 0.8 ns 3 tw(CKO2L) Pulse duration, CLKOUT2 low (C2/2) – 0.8 (C2/2) + 0.8 ns 4 tt(CKO2) Transition time, CLKOUT2 2 ns (1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. (2) C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period divide-by-2. Figure 11-6. CLKOUT2 Submit Documentation Feedback PARAMETRIC INFORMATION 87 |
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