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TC1411NEPA Datasheet(PDF) 1 Page - TelCom Semiconductor, Inc |
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TC1411NEPA Datasheet(HTML) 1 Page - TelCom Semiconductor, Inc |
1 / 5 page 4-189 TELCOM SEMICONDUCTOR, INC. 7 6 5 4 3 1 2 8 1A HIGH-SPEED MOSFET DRIVERS TC1411 TC1411N ORDERING INFORMATION Part No. Package Temp. Range TC1411COA 8-Pin SOIC 0 °C to +70°C TC1411CPA 8-Pin Plastic DIP 0 °C to +70°C TC1411EOA 8-Pin SOIC – 40 °C to +85°C TC1411EPA 8-Pin Plastic DIP – 40 °C to +85°C TC1411NCOA 8-Pin SOIC 0 °C to +70°C TC1411NCPA 8-Pin Plastic DIP 0 °C to +70°C TC1411NEOA 8-Pin SOIC – 40 °C to +85°C TC1411NEPA 8-Pin Plastic DIP – 40 °C to +85°C FUNCTIONAL BLOCK DIAGRAM OUTPUT INPUT GND EFFECTIVE INPUT C = 10pF 300mV INVERTING OUTPUTS NONINVERTING OUTPUTS VDD TC1411N 4.7V TC1411 FEATURES s Latch-Up Protected: Will Withstand 500mA Reverse Current s Input Will Withstand Negative Inputs Up to 5V s ESD Protected .................................................... 4 kV s High Peak Output Current .................................. 1A s Wide Operating Range .......................... 4.5V to 16V s High Capacitive Load Drive Capability .......................... 1000pF in 25nsec s Short Delay Time .................................. 30nsec Typ s Consistent Delay Times With Changes in Supply Voltage s Matched Delay Times s Low Supply Current — With Logic “1” Input ................................. 500 µA — With Logic “0” Input ................................. 150 µA s Low Output Impedance ....................................... 8 Ω s Pinout Same as TC1410/12/13 GENERAL DESCRIPTION The TC1411/1411N are 1A CMOS buffer/drivers. They will not latch up under any conditions within their power and voltage ratings. They are not subject to damage when up to 5V of noise spiking of either polarity occurs on the ground pin. They can accept, without damage or logic upset, up to 500 mA of current of either polarity being forced back into their output. All terminals are fully protected against up to 4 kV of electrostatic discharge. As MOSFET drivers, the TC1411/1411N can easily switch 1000 pF gate capacitance in 25nsec with matched rise and fall times, and provide low enough impedance in both the ON and the OFF states to ensure the MOSFET’s intended state will not be affected, even by large transients. The rise and fall time edges are matched to allow driving short-duration inputs with greater accuracy. PIN CONFIGURATIONS TC1411 1 2 3 4 VDD 5 6 7 8 OUT GND VDD IN NC GND NC = NO INTERNAL CONNECTION 2 6, 7 INVERTING NOTE: SOIC pinout is identical to DIP. OUT TC1411N 1 2 3 4 VDD 5 6 7 8 OUT GND VDD IN NC GND 2 6, 7 NONINVERTING OUT TC1411/N-10 10/11/96 |
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