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TELCOM SEMICONDUCTOR, INC.

5V PRECISION DATA ACQUISITION

SUBSYSTEMS

TC530

TC534

PIN DESCRIPTION (Cont.)

Pin No.

Pin No.

Pin No

Pin No.

(TC530

(TC530

(TC534

(TC534

28-Pin

28-Pin

40-Pin

44-Pin

PDIP, 300 Mil.)

SOIC)

PDIP)

PQFP)

Symbol

Description

15

15

22

19

Analog Input. This pin connects to the other side of the

be clocked from an external frequency source connected to

this pin. The external frequency source must be a pulse wave

form with a minimum 30% duty cycle and rise and fall times

must be left floating. A maximum operating frequency of 2MHz

(crystal) or 4MHz (external clock source) is permitted.

16

16

23

20

Logic Level Output. Serial port data output pin. This pin is

enabled only when R/W is high.

17

17

24

21

Logic Input, Positive and Negative Edge Triggered. Serial port

clock. When R/W is high, serial data is clocked out of the

18

18

25

22

Logic Level Input. Serial port input pin. The A/D converter

determined by the LOAD VALUE byte clocked into this pin.

This initialization must take place at power up, and can be

rewritten (or modified and rewritten) at any time. The LOAD

19

19

26

23

R/W

Logic Level Input. This pin must be brought low to perform a

write to the serial port (e.g. initialize the A/D converter). The

20

20

27

24

EOC

Open Drain Output. End-of-Conversion (EOC) is asserted

any time the TC530/534 is in the AZ phase of conversion. This

occurs when either the TC530/534 initiates a normal AZ phase,

or when RESET is pulled high. EOC is returned high when the

TC530/534 exits AZ. Since EOC is driven low immediately

following completion of a conversion cycle, it can be used as

a DATA READY processor interrupt.

21

21

30

28

RESET

Logic Level Input. It is necessary to force the TC530/534 into

the Auto Zero phase when power is initially applied. This is

accomplished by momentarily taking RESET high. Using an I/O

port line from the microprocessor, or by applying an external

system reset signal, or by connecting a 0.01

µF capacitor from

Conversions are performed continuously as long as RESET is

low and conversion is halted when RESET is high. RESET

may therefore be used in a complex system to momentarily

suspend conversion (for example while the address lines of an

input multiplexer are changing state). In this case, RESET

should be pulled high only when the EOC is LOW to avoid

excessively long integrator discharge times which could result in

erroneous conversion (see

Applications Section).