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LF4415 Datasheet(PDF) 9 Page - LUXPIA

No. de pieza LF4415
Descripción Electrónicos  Video Memory / FIFO
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Fabricante Electrónico  LUXPIA [LUXPIA]
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LF4415 Datasheet(HTML) 9 Page - LUXPIA

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Depth
Expansion
LOGIC Devices Incorporated
www.logicdevices.com
January 23, 2008 LDS-44xx-A
High Performance Memory Product
9
MEMORY
FRAME
Video Memory / FIFO
LF4460
LF4430
LF4415
PRELIMINARY
Device Configuration
There are four operations that can be performed between the master and the slave. They are: Write to
consecutive registers, write to a single control register, read from consecutive registers and read from a
single register. To write to consecutive control registers, a start signal and base address must be sent
with the R/W bit as described above. After the acknowledgment back from the appropriate slave, the
8-bit address of the target control register must be written to the slave with the R/W bit LOW. The slave
then acknowledges by setting SDA LOW. The data byte to be written into the register can now be
transferred on SDA. The slave then acknowledges by pulling SDA LOW on the next positive going pulse
of SCL. The first control register address loaded into the LF4430 is considered as the beginning address
for consecutive writes, and automatically increments to the next higher address space. Therefore after the
acknowledgement, the data byte to configure register (first address + 1) can now be transferred from master
to slave. At any point a stop signal can be given to end the data transfer. To write to a single control register,
the same technique can be applied adding a stop signal after the first data write.
To read from consecutive control registers, the master must again give the start signal followed by a
base address with the R/W bit = 0, as if the master wants to write to the slave. The appropriate slave
then acknowledges. The master will then transfer the target register address to the slave and wait for
an acknowledge. The master will then give a repeated start signal to the slave, along with the base
address and R/W bit this time HIGH signifying a read and wait for an acknowledge. The user must write
to the LF44xx to select the appropriate initial target register. Otherwise the starting position of the read is
uncertain. Once the LF44xx acknowledges, the next byte of data on SDA is the contents of the addressed
register sent from the device. If the master acknowledges, the LF44xx will send the next higher register’s
contents on the following byte of data. To read from only one register is the same procedure as for
consecutive reading with a stop signal following the transfer of the register’s contents.
**NOTE: UPDATE COMMAND REQUIRED
After updating any of the configuration registers, Register 03F must be written
with all zeros to modify the working registers.
Depth Expansion Mode
Multiple devices can be cascaded for depth expansion - deepening the address space by 2x, 3x, etc. The
address space is extended for every additional device that is cascaded. Depth expansion is implemented
by tying together input data, controls, and outputs of all devices. Only one device drives the shared output
bus at a time. All bus contention, addressing, and inter-chip control is handled internally. No additional
external circuitry is required.
Each device in an expansion of N devices is responsible for 1/N of the address space. That is, each
device writes and/or reads based on common W/R pointer locations and its position in the expansion.
Configuration Register C[3:0] (BASE_ADDR) is used to define each device’s position in the chain of
devices.
Depth expansion is supported in single-channel mode only. The configuration registers of each device
must be programmed identically, depending on mode/function, except for Register C. Register C defines
which region of the 24bit address space the particular device is responsible for. Within Register C, there
is a 4bit BASE_ADDR and 4bit NUM_DEV word. BASE_ADDR determines the region of address space
each device controls, and NUM_DEV defines how many devices are tied together. Register C effectively
is programmed as “Chip n of N”.


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