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CD74HC4059E Datasheet(PDF) 2 Page - Texas Instruments |
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CD74HC4059E Datasheet(HTML) 2 Page - Texas Instruments |
2 / 7 page 2 The counter should always be put in the master preset mode before the ÷5 mode is selected. Whenever the master preset mode is used, control signals Kb = “low” and Kc = “low” must be applied for at least 3 full clock pulses. After Preset Mode inputs have been changed to one of the ÷ modes, the next positive-going clock transition changes an internal flip-flop so that the countdown can begin at the second positive-going clock transition. Thus, after an MP (Master Preset) mode, there is always one extra count before the output goes high. Figure 1 illustrates a total count of 3 ( ÷8 mode). If the Master Preset mode is started two clock cycles or less before an output pules, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the “Jam” count when the output pulse appears. A “high” on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to “low”. If the Latch Enable is “low”, the output pulse will remain high for only one cycle of the clock-input signal. Pinout CD74HC4059 (PDIP) TOP VIEW Functional Diagram 1 2 3 4 5 6 7 8 9 10 11 12 CP LE J1 J2 J3 J4 J16 J15 J14 J13 Kc GND 16 17 18 19 20 21 22 23 24 15 14 13 VCC J5 J6 J7 J8 J10 J12 Ka Kb Q J9 J11 Q = Kc LE Kb Ka CP J1 - J16 f IN N ------- TRUTH TABLE MODE SELECT INPUT FIRST COUNTING SECTION LAST COUNTING SECTION COUNTER RANGE DESIGN EXTENDED Ka Kb Kc MODE DIVIDES-BY CAN BE PRESET TO A MAX OF: (NOTE 3) JAM INPUTS USED: MODE DIVIDES-BY CAN BE PRESET TO A MAX OF: (NOTE 3) JAM INPUTS USED: MAX MAX H H H 2 1 J1 8 7 J2, J3, J4 15,999 17,331 L H H 4 3 J1, J2 4 3 J3, J4 15,999 18,663 HLH 5 (Note 4) 4 J1, J2, J3 2 1 J4 9,999 13,329 L L H 8 7 J1, J2, J3 2 1 J4 15,999 21,327 H H L 10 9 J1, J2, J3, J4 1 0 - 9,999 16,659 X L L Master Preset Master Preset - - NOTES: 2. X = Don’t Care 3. J1 = Least Significant Bit. J4 = Most Significant Bit. 4. Operation in the ÷5 mode (1st counting section) requires going through the Master Preset mode prior to going into the ÷5 mode. At power turn-on, Kc must be “low” for a period of 3 input clock pulses after VCC reaches a minimum of 3V. CD74HC4059 CD74HC4059 |
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