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SN74ABT162841DGG Datasheet(PDF) 1 Page - Texas Instruments

No. de pieza SN74ABT162841DGG
Descripción Electrónicos  20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74ABT162841DGG Datasheet(HTML) 1 Page - Texas Instruments

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SN54ABT162841, SN74ABT162841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS665B – JUNE 1996 – REVISED MAY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
™ Family
D Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D High-Impedance State During Power Up
and Power Down
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 20-bit transparent D-type latches feature
noninverting 3-state outputs designed specifically
for
driving
highly
capacitive
or
relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The ’ABT162841 can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The outputs, which are designed to sink up to 12 mA, include equivalent 25-
Ω series resistors to reduce
overshoot and undershoot.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Copyright
© 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-
ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABT162841 . . . WD PACKAGE
SN74ABT162841 . . . DGG OR DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE


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