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ADSD-1402

4

THERMAL REQUIREMENTS

The ADSD-1402 sampling A/D converter is fully characterized

and specified over the commercial operating temperature

(ambient) range of 0 to +70°C (MC suffix) and military

temperature range of –55 to +125°C (MM suffix). All room-

without the use of heat sinks or forced-air cooling. Thermal

impedance figures for each device are listed in their

respective specification tables.

These devices do not normally require heat sinks, however,

standard precautionary design and layout procedures should be

used to ensure devices do not overheat. The ground and power

planes beneath the package, as well as all pcb signal runs to

and from the device, should be as heavy as possible to help

conduct heat away from the package. Electrically-insulating,

thermally-conductive "pads" may be installed underneath the

package. Devices should be soldered to boards rather than

"socketed", and of course, minimal air flow over the surface can

greatly help reduce the package temperature.

In more severe ambient conditions, the package/junction

temperature of a given device can be reduced dramatically

(typically 35%) by using one of DATEL's HS Series heat sinks.

See Ordering Information for the assigned part number.

Request DATEL Application Note AN-8, "Heat Sinks for DIP

Data Converters", or contact DATEL directly, for additional

information.

Figure 3. ADSD-1402 Connection Diagram

Notes:

➀ Recommended to use same supply source for +5 Analog and +5 Digital. Try using as clean of a supply as possible (Bypass caps., 10uF and .1uF).

➁ Outputs are enabled by either turning ENABLE A (Pin 10) or ENABLE B

(Pin 31) low for prespective analog inputs A or B. A high on ENABLE A or ENABLE B results in disabling the output bus (High Z).

A D S D - 1 4 0 2

2 9

2 8

2 7

2 6

2 5

2 4

2 3

2 2

1 9

1 8

1 7

1 6

1 5

1 4

1 3

B I T 1 ( M S B )

B I T 2

B I T 3

B I T 4

B I T 5

B I T 6

B I T 7

B I T 8

B I T 9

B I T 1 0

B I T 1 1

B I T 1 2

B I T 1 3

B I T 1 4 ( L S B )

0 . 1 µ F

S t a r t A

7

6

1 1

5

3 1

E n a b l e B

3 4 , 3 5

1 0 u F

. 1 u F

– 5 V

1 0 u F

. 1 u F

+ 5 V

9 , 3 2

2 , 1 2 , 3 9

E n a b l e A 1 0

S W 1

+ 5 V

S W 2

S t a r t B

3 0

1 0 K

1 0 K

1 0 K

1 0 K

– 5 V

+ 5 V

I n p u t A

I n p u t B

3 , 8 , 2 0 , 2 1 , 3 3 , 3 8 G N D

1

4 0

4 G a i n A

I n B

I n A

2 . 5 V R E F .

R a n g e

O f f s e t A

3 6 O f f s e t B

3 7 G a i n B

1 0 u F

N / C

E O C

R 1

R 2

R 3

R 4

+ 5 V

See timing diagram for details.