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SN74ACT8997NT Datasheet(PDF) 11 Page - Texas Instruments |
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SN74ACT8997NT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 28 page SN54ACT8997, SN74ACT8997 SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS SCAS157D – APRIL 1990 – REVISED DECEMBER 1996 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Bit 4 – Parity Mask The signal IRERR can be masked from appearing on DCO even if bits 6 and 5 are set such that it is output in the Pause-IR state (reset condition = do not mask IRERR). Bit – DCO Drive Select DCO can be configured as either an open-drain or 3-state output (reset condition = open drain). The open-drain configuration allows multiple DCO outputs to be used in a wired-OR or wired-AND application. The 3-state configuration allows the DCO output to be connected to a bus. Bit 2 – DCO Enable When configured as a 3-state output, DCO can be placed in the high-impedance state (reset condition = disabled). If configured as an open-drain output and disabled, DCO outputs a high level. Bit 1 – DCI Polarity Select DCI can be configured as an active-low or active-high input (reset condition = active low). Bit 0 – Device Test Pins Output Enable (active low) DTCK, DTDO1–4, and DTMS1–4 pins can be placed in the high-impedance state (disabled) with this bit (reset condition = not disabled). If DTDO1–4 pins are not disabled using this control bit, then their drive state is dependent on the value of the select register (see Table 7). Several CTLR bits affect the functionality of the DCO output. The DCO function table is given in Table 6. Figure 3 illustrates the order of scan for the CTLR. Bit 9 (MSB) TDI or DTDI Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 3. Control-Register Bits and Order of Scan |
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