SN54GTL16616, SN74GTL16616

17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

WITH BUFFERED CLOCK OUTPUTS

SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999

6

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

SN54GTL16616

SN74GTL16616

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

95

95

MHz

t

Pulse duration

LEAB or LEBA high

3.3

3.3

ns

tw

Pulse duration

CLKAB or CLKBA high or low

5.5

5.5

ns

A before CLKAB

↑

1.3

1.3

B before CLKBA

↑

2.5

2.5

t

Setup time

A before LEAB

↓

0

0

ns

tsu

Setup time

B before LEBA

↓

1.1

1.1

ns

CEAB before CLKAB

↑

2.2

2.2

CEBA before CLKBA

↑

2.7

2.7

A after CLKAB

↑

1.6

1.6

B after CLKBA

↑

0.4

0.4

th

Hold time

A after LEAB

↓

4

4

ns

th

Hold time

B after LEBA

↓

3.5

3.5

ns

CEAB after CLKAB

↑

1.1

1.1

CEBA after CLKBA

↑

0.9

0.9

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.