SN54HC175, SN74HC175

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS299A – JANUARY 1996 – REVISED MAY 1997

4

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC175

SN74HC175

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

0

6

0

4.2

0

5

fclock

Clock frequency

4.5 V

0

31

0

21

0

25

MHz

6 V

0

36

0

25

0

29

2 V

80

120

100

CLR low

4.5 V

16

24

20

t

Pulse duration

6 V

14

20

17

ns

tw

Pulse duration

2 V

80

120

100

ns

CLK high or low

4.5 V

16

24

20

6 V

14

20

17

↑

2 V

100

150

125

↑

Data

4.5 V

20

30

25

t

Setup time before CLK

↑

6 V

17

25

21

ns

tsu

Setup time before CLK

↑

2 V

100

150

125

ns

CLR inactive

4.5 V

20

30

25

6 V

17

25

21

↑

2 V

0

0

0

th

Hold time, data after CLK

↑

4.5 V

0

0

0

ns

6 V

0

0

0

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HC175

SN74HC175

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

12

4.2

5

fmax

4.5 V

31

50

21

25

MHz

6 V

36

60

25

29

2 V

52

150

255

190

CLR

Any

4.5 V

15

30

45

38

t d

6 V

13

26

38

32

ns

tpd

2 V

58

150

255

190

ns

CLK

Any

4.5 V

16

30

45

38

6 V

13

26

38

32

2 V

38

75

110

90

tt

Any

4.5 V

8

15

22

19

ns

6 V

6

13

19

16

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

No load

30

pF