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ADP3419 Datasheet(PDF) 3 Page - ON Semiconductor

No. de pieza ADP3419
Descripción Electrónicos  Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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ADP3419
Rev. 2 | Page 3 of 13 | www.onsemi.com
SPECIFICATIONS
VCC = SD = 5 V, BST = 4 V to 26 V, TA = 0°C to 100°C, unless otherwise noted.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR)
Input Voltage High
VIH
2.0
V
Input Voltage Low
VIL
0.8
V
Input Current
IIN
Inputs = 0 V or 5 V
−1
+1
μA
DRVLSD Propagation Delay Time
tpdl
DRVLSD,
tpdh
DRVLSD
CLOAD = 3 nF, Figure 3
20
ns
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
BST − SW = 4.6 V
1.7
3.3
Ω
Output Resistance, Sinking Current
BST − SW = 4.6 V
0.8
2.3
Ω
Transition Times
trDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
14
35
ns
tfDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
11
25
ns
Propagation Delay Times1
tpdhDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
15
32
70
ns
tpdlDRVH
BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4
28
60
ns
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
1.7
3.3
Ω
Output Resistance, Sinking Current
0.8
2.3
Ω
Transition Times
trDRVL
CLOAD = 3 nF, Figure 4
13
30
ns
tfDRVL
CLOAD = 3 nF, Figure 4
11
25
ns
Propagation Delay Times1, 2
tpdhDRVL
CLOAD = 3 nF, Figure 4
25
48
ns
tpdlDRVL
CLOAD = 3 nF, Figure 4
16
30
ns
SW Transition Timeout2
tSWTO
BST − SW = 4.6 V
150
350
600
ns
Zero-Crossing Threshold
VZC
1
V
SUPPLY
Supply Voltage Range
VCC
4.6
6
V
Supply Current
Normal Mode
ISYS(NM)
ICC + IBST, IN = 0 V or 5 V
0.8
1.5
mA
Shutdown Mode
ISYS(SD)
ICC + IBST, SD = 0 V
325
600
μA
Undervoltage Lockout Threshold
VCC rising
3.8
4.25
4.5
V
Undervoltage Lockout Hysteresis3
VCC falling
50
120
mV
1 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%.
2 The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO.
3 Guaranteed by characterization, not production tested.


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