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CAT9534YI-GT2 Datasheet(PDF) 11 Page - ON Semiconductor

No. de pieza CAT9534YI-GT2
Descripción Electrónicos  8-bit I짼C and SMBus I/O Port with Interrupt
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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CAT9534YI-GT2 Datasheet(HTML) 11 Page - ON Semiconductor

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CAT9534
© 2009 SCILLC. All rights reserved
11
Doc. No. MD-9004 Rev. C
Characteristics subject to change without notice
INTERRUPT OUTPUT
CAT9534’s interrupt otuput is an active LOW open-
drain output that is activated when any port pin
configured as an input changes state. The interrupt
output is reset when the input returns to its previous
state or the Input Port Register is read.
Note that changing an I/O from an output to an input
may cause a false interrupt to occur if the state of
the pin does not match the contents of the Input Port
register.
POWER-ON RESET OPERATION
When the power supply is applied to VCC pin, an
internal power-on reset pulse holds the CAT9534 in
a reset state until VCC reaches VPOR level. At this
point, the reset condition is released and the internal
state machine and the CAT9534’s registers are
initialized to their default state.
Figure 10. Read from Register
Figure 11. Read Input Port Register
DATA
S
0
100
A2
A0
0
A
A1
0
1
0
0
A2 A1 A0
A
DATA
A
acknowledge
from master
acknowledge from slave
R/W
slave address
slave address
data from register
COMMAND BYTE
AS
1
acknowledge from slave
acknowledge from slave
R/W
At this moment master-transmitter becomes
master-receiver and slave-receiver
becomes slave-transmitter
NA
no acknowledge
from master
data from register
P
last byte
first byte
12
3
4
5
6
7
8
9
SCL
SDA
READ FROM
PORT
DATA INTO
PORT
S
010
0
A2
A0
1
A
A1
A
DATA 4
NA
P
no acknowledge
from master
acknowledge
from master
acknowledge
from slave
R/W
slave address
data from port
start condition
stop
condition
DATA 2
tPS
tPH
DATA 3
DATA 4
DATA 1
data from port
tIV
tIR
INT
DATA 1


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