CAT9555HV6I-GT2 datasheet(9/17 Pages) ONSEMI

No. de pieza	CAT9555HV6I-GT2

Descripción Electrónicos	16-bit I짼C and SMBus I/O Port with Interrupt

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Fabricante Electrónico	ONSEMI [ON Semiconductor]

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CAT9555

9

Doc. No. MD-9003, Rev. I

Characteristics subject to change without notice

FUNCTIONAL DESCRIPTION

The CAT9555 general purpose input/output (GPIO)

peripheral provides up to sixteen I/O ports, controlled

through an I²C compatible serial interface

The CAT9555 supports the I²C Bus data transmission

protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master

device which generates the serial clock and all

START and STOP conditions for bus access. The

CAT9555 operates as a Slave device. Both the

Master device and Slave device can operate as either

transmitter or receiver, but the Master device controls

which mode is activated.

I²C BUS PROTOCOL

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is

high will be interpreted as a START or STOP

condition (Figure 5).

START AND STOP CONDITIONS

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT9555 monitors the

SDA and SCL lines and will not respond until this

condition is met.

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

DEVICE ADDRESSING

After the bus Master sends a START condition, a

slave address byte is required to enable the CAT9555

for a read or write operation. The four most significant

bits of the slave address are fixed as binary 0100

(Figure 6). The CAT9555 uses the next three bits as

address bits.

The address bits A2, A1 and A0 are used to select

which device is accessed from maximum eight

devices on the same bus. These bits must compare to

their hardwired input pins. The 8th bit following the 7-

bit slave address is the R/W

¯¯ bit that specifies whether

a read or write operation is to be performed. When

this bit is set to “1”, a read operation is initiated, and

when set to “0”, a write operation is selected.

Following the START condition and the slave address

byte, the CAT9555 monitors the bus and responds

with an acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

CAT9555 then performs a read or a write operation

depending on the state of the R/W

¯¯ bit.

Figure 5. START/STOP Condition

Figure 6. CAT9555 Slave Address

0

1

0

A2A1A0

R/W

SLAVE ADDRESS

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

START

CONDITION

STOP

CONDITION

SDA

SCL

Número de pieza similar - CAT9555HV6I-GT2

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Catalyst Semiconductor	CAT9555HV6I-GT2	235Kb / 17P	16-bit I2C and SMBus I/O Port with Interrupt
ON Semiconductor	CAT9555HV6I-GT2	389Kb / 18P	16-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9003, Rev. J
ON Semiconductor	CAT9555HV6I-GT2	176Kb / 16P	16-bit I2C and SMBus I/O Port with Interrupt June, 2011 ??Rev. 11

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Descripción similar - CAT9555HV6I-GT2

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
ON Semiconductor	CAT9555	389Kb / 18P	16-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9003, Rev. J
	CAT9534	172Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9004 Rev. D
	CAT9554WI-G	184Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9002, Rev. F
	CAT9534WI-G	244Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9004 Rev. C
	CAT9554	209Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9002, Rev. F
Catalyst Semiconductor	CAT9555	212Kb / 17P	16-bit I2C and SMBus I/O Port with Interrupt
NXP Semiconductors	PCA9555	185Kb / 22P	16-bit I2C and SMBus I/O port with interrupt 2004 Sep 30
Catalyst Semiconductor	CAT9555	235Kb / 17P	16-bit I2C and SMBus I/O Port with Interrupt
ON Semiconductor	CAT9555	176Kb / 16P	16-bit I2C and SMBus I/O Port with Interrupt June, 2011 ??Rev. 11
NXP Semiconductors	PCA9555	583Kb / 34P	16-bit I2C-bus and SMBus I/O port with interrupt Rev. 08-22 October 2009

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CAT9555HV6I-GT2 Datasheet(PDF) 9 Page - ON Semiconductor

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Descripción similar - CAT9555HV6I-GT2

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