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ADG1604BRUZ-REEL Datasheet(PDF) 9 Page - Analog Devices

No. de pieza ADG1604BRUZ-REEL
Descripción Electrónicos  1 廓 Typical On Resistance, 짹5 V, 12 V, 5 V, and 3.3 V, 4:1 Multiplexer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADG1604BRUZ-REEL Datasheet(HTML) 9 Page - Analog Devices

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ADG1604
Rev. 0 | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1604
NC = NO CONNECT
1
2
3
4
5
6
7
EN
VSS
S1
NC
D
S2
A0
14
13
12
11
10
9
8
GND
VDD
S3
NC
NC
S4
A1
TOP VIEW
(Not to Scale)
Figure 2. 14-Lead TSSOP Pin Configuration
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
1
VSS
2
NC
3
S1
4
S2
11 VDD
12 GND
10 S3
9S4
TOP VIEW
(Not to Scale)
ADG1604
Figure 3. 16-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
TSSOP
LFCSP
1
15
A0
Logic Control Input.
2
16
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, the Ax logic inputs determine the on switch.
3
1
VSS
Most Negative Power Supply Potential.
4
3
S1
Source Terminal. This pin can be an input or output.
5
4
S2
Source Terminal. This pin can be an input or output.
6
6
D
Drain Terminal. This pin can be an input or output.
7, 8, 9
2, 5, 7, 8, 13
NC
No Connection.
10
9
S4
Source Terminal. This pin can be an input or output.
11
10
S3
Source Terminal. This pin can be an input or output.
12
11
VDD
Most Positive Power Supply Potential.
13
12
GND
Ground (0 V) Reference.
14
14
A1
Logic Control Input.
N/A
17 (EPAD)
EP (EPAD)
Exposed Pad. Tied to substrate, VSS.
Table 8. ADG1604 Truth Table
EN
A1
A0
S1
S2
S3
S4
0
X
X
Off
Off
Off
Off
1
0
0
On
Off
Off
Off
1
0
1
Off
On
Off
Off
1
1
0
Off
Off
On
Off
1
1
1
Off
Off
Off
On


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