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TLC1549 Datasheet(PDF) 11 Page - Texas Instruments |
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TLC1549 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 15 page TLC1549C, TLC1549I, TLC1549M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS059C – DECEMBER 1992 – REVISED MARCH 1995 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Sample Cycle B A/D Conversion Interval Initialize Initialize MSB LSB Previous Conversion Data B9 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z State 12 3 4567 89 10 1 I/O CLOCK DATA OUT CS (see Note A) ( ≤ 21 µs) Figure 6. Timing for 10-Clock Transfer Using CS Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data B9 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level 12 3 4 5 6 7 8 9 10 1 I/O CLOCK DATA OUT CS Initialize (see Note A) Must Be High on Power Up ( ≤ 21 µs) See Note C Figure 7. Timing for 10-Clock Transfer Not Using CS Sample Cycle B A/D Conversion Interval Initialize MSB LSB Previous Conversion Data B9 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 12 3 4 5 6 7 8 9 10 1 I/O CLOCK DATA OUT CS Initialize Low Level Hi-Z See Note B 11 16 (see Note A) ( ≤ 21 µs) Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs) NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock after CS ↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup time has elapsed. B. A low-to-high transition of CS disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. C. The first I/O CLOCK must occur after the end of the previous conversion. |
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