TPS1120, TPS1120Y

DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

2

POST OFFICE BOX 655303

schematic

1GATE

1SOURCE

1DRAIN†

ESD-

Protection

Circuitry

2GATE

2SOURCE

2DRAIN†

ESD-

Protection

Circuitry

† For all applications, both drain pins for each device should be connected.

TPS1120Y chip information

This chip, when properly assembled, displays characteristics similar to the TPS1120C. Thermal compression

or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with

conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL

BONDING PADS: 4

× 4 MILS MINIMUM

TJmax = 150°C

TOLERANCES ARE

±10%

ALL DIMENSIONS ARE IN MILS

TPS1120Y

(2)

(6)

(1)

(3)

(7)

(8)

(5)

(4)

1DRAIN

1SOURCE

1GATE

2SOURCE

2GATE

1DRAIN

2DRAIN

2DRAIN

57

64

(2)

(1)

(3)

(4)

(6)

(7)

(8)

(5)