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ADS62P29 Datasheet(PDF) 11 Page - Texas Instruments

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No. de pieza ADS62P29
Descripción Electrónicos  Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

ADS62P29 Datasheet(HTML) 11 Page - Texas Instruments

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ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com............................................................................................................................................................. SLAS635A – APRIL 2009 – REVISED JUNE 2009
TIMING REQUIREMENTS – LVDS AND CMOS MODES (continued)
Typical values are at 25°C, AVDD = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, 1.5 Vpp
clock amplitude, CLOAD = 5pF , RLOAD = 100Ω , (unless otherwise noted).
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.7V to
1.9V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output buffer enable (OE)
tOE
Time to valid data after output buffer becomes active
100
ns
to data delay
Table 1. LVDS Timings at Lower Sampling Frequencies
Setup Time, ns
Hold Time, ns
Sampling Frequency, MSPS
MIN
TYP
MAX
MIN
TYP
MAX
210
0.75
1.1
0.75
1.15
185
0.9
1.25
0.85
1.25
153
1.15
1.55
1.1
1.5
125
1.6
2
1.45
1.85
< 100
2
2
Enable LOW SPEED mode
tPDI, ns
1
≤ Fs ≤ 100
MIN
TYP
MAX
Enable LOW SPEED mode
12.6
Table 2. CMOS Timings at Lower Sampling Frequencies
Timings Specified With Respect to Input Clock
Sampling Frequency, MSPS
tSTART, ns
Data Valid time, ns
MIN
TYP
MAX
MIN
TYP
MAX
210
2.5
1.7
2.7
190
1.9
2
3
170
0.9
2.7
3.7
150
6
3.6
4.6
Timings Specified With Respect to CLKOUT
Sampling Frequency, MSPS
Setup Time, ns
Hold Time, ns
MIN
TYP
MAX
MIN
TYP
MAX
170
2.1
3.7
0.35
1.0
150
2.8
4.4
0.5
1.2
125
3.8
5.4
0.8
1.5
<100
5
1.2
Enable LOW SPEED mode
tPDI, ns
1
≤ Fs ≤ 100
MIN
TYP
MAX
Enable LOW SPEED mode
9
Copyright © 2009, Texas Instruments Incorporated
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