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ADS1675IPAGR Datasheet(PDF) 7 Page - Texas Instruments |
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ADS1675IPAGR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 36 page t LSCLKDC DRDY MSB LSB MSB D UT O S LK C t LSCLKDR t LDOPD t LDRPW t LSCLK TIMING REQUIREMENTS: High-Speed LVDS CLK SCLK START DRDY t STCLK t LSCLKDR t LSCLK t LCLKSCLK t SETTLE t LPLLSTL t CLK t SETTLE ADS1675 www.ti.com .................................................................................................................................................. SBAS416B – DECEMBER 2008 – REVISED JUNE 2009 TIMING CHARACTERISTICS (1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101. Figure 1. High-Speed LVDS Data Retrieval Timing At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V. SYMBOL DESCRIPTION MIN TYP MAX UNIT tLDRPW DRDY pulse width 2 4 tLSCLKs tLSCLKDR SCLK to DRDY delay 2 3 ns tLDOPD Valid data delay time from serial shift clock 1.5 2.5 ns tLSCLK Period of LVDS serial shift clock (SCLK) 0.33 tCLKs tLSCLKDC Shift clock duty cycle 47 53 % tCLK CLK period (1/fCLK) 31.25 ns tLCLKSCLK Delay from rising edge of CLK to rising edge of SCLK 13 20 ns tLPLLSTL PLL settling time 80 µs tSTCLK Setup time, rising edge of START to falling edge of CLK –3 3 ns tSETTLE Digital filter settling time See Table 5 and Table 6 Figure 2. PLL Timing Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS1675 |
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