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TPS53126RGET Datasheet(PDF) 9 Page - Texas Instruments |
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TPS53126RGET Datasheet(HTML) 9 Page - Texas Instruments |
9 / 30 page DETAILED DESCRIPTION PWM OPERATION DRIVERS PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL 5 VOLT REGULATOR SOFT START PRE-BIAS SUPPORT TPS53126 www.ti.com........................................................................................................................................................................................................ SLUS909 – MAY 2009 The main control loop of the TPS53126 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 Mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP mode control. Each SMPS of the TPS53126 contains 2 high-current resistive MOSFET drivers. The Low-side driver is a ground referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET whose source is connected to PGND. The High-side Driver is a floating SW referenced VBST powered driver designed to drive the gate of a high-current, low RDS(on) N-channel MOSFET. To maintain the BST voltage during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to Gate Charge (Qg AT Vgs = 5V) times Switching Frequency (fsw). To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the inductor current is carried by one of the MOSFETs body diodes. The TPS53126 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS53126 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant. The TPS53126 has an internal 5V Low-Dropout (LDO) Regulator to provide a regulated voltage for all four drivers and the ICs internal logic. A capacitor from VREG5 to GND is required to stabilize the internal regular. An internal 10 Ω resistor from VREG5 filters the regulator output to the IC’s analog and logic input voltage, V5FILT. An additional capacitor is required from V5FILT to GND to filter switching noise from VREG5. The TPS53126 has an internal, 1.2ms, voltage servo soft-start for each channel. When the ENx pin becomes high, an internal DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is maintained during start up. As the TPS53126 shares one DAC with both channels, if ENx pin is set to high while another channel is starting up, soft start is postponed until another channel soft start has completed. If both of EN1 and EN2 are set high at a same time, both channels start up at same time. The TPS53126 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), then the TPS53126 slowly activates synchronous rectification by limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS53126 |
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