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TPS53126PW Datasheet(PDF) 6 Page - Texas Instruments |
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TPS53126PW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page DEVICE INFORMATION TPS53126 SLUS909 – MAY 2009........................................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (Unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT TCITRIP ITRIP temperature coefficient On the basis of 25°C(2) 4000 ppm/°C (VTRIPx-GND-VPGNDx-SWx) voltage, –15 0 15 VTRIPx-GND = 60 mV, TA = 25°C VOCLoff OCP compensation offset mV (VTRIPx-GND-VPGNDx-SWx) voltage, –20 20 VTRIPx-GND = 60 mV Current limit threshold setting VRtrip VTRIPx-GND voltage 30 300 mV range OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP Output OVP trip threshold OVP detect 110% 115% 120% TOVPDEL Output OVP prop delay time 1.5 µs UVP detect 65% 70% 75% VUVP Output UVP trip threshold Hysteresis (recovery < 20 µs) 10% TUVPDEL Output UVP delay time 17 30 40 µs TUVPEN Output UVP enable delay time UVP enable delay 1.2 2 2.5 ms THERMAL SHUTDOWN Shutdown temperature(3) 150 TSDN Thermal shutdown threshold °C Hysteresis(3) 20 (2) Ensured by design. Not production tested. (3) Ensured by design. Not production tested. PIN FUNCTIONS PIN I/O DESCRIPTION QFN TSSOP NAME 24 24 Supply input for high-side NFET driver (Boost Terminal). Bypass to SWx with a VBST1, 23, 8 2, 11 I high-quality 0.1 µF ceramic capacitor. An external schottky diode can be added if forward VBST2 drop is critical to drive the high-side FET. EN1, EN2 24, 7 3, 10 I Channel 1 and channel 2 high level enable pins. Output voltage inputs for on-time adjustment and output discharge. Connect directly to the VO1, VO2 1, 6 4, 9 I output voltage. VFB1, 2, 5 5, 8 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider. VFB2 GND 3 6 I Signal ground pin. Connect to PGND1, PGND2 and system ground at a single point. DRVH1, High-side MOSFET gate driver outputs. SWx referenced drivers switch between SWx 22, 9 1, 12 O DRVH2 (OFF) and VBSTx (ON). SW1, SW2 21, 10 24, 13 I/O Switch node connections for both the high-side drivers and the current comparators. DRVL1, Low-side MOSFET gate driver outputs. PGND referenced drivers switch between PGNDx 20, 11 23, 14 O DRVL2 (OFF) and VREG5 (ON). PGND1, Power ground connections for both the low-side drivers and the current comparators. 19, 12 22, 15 I/O PGND2 Connect PGND1, PGND2 and GND strongly together near the IC. TRIP1, Over current trip point programming pin. Connect to GND with a resistor to GND to set 18, 13 21, 16 I TRIP2 threshold for low-side RDS(on) current limit. VIN 17 20 I Supply Input for 5V linear regulator. 5V supply input for the entire control circuit except the MOSFET drivers. Bypass to GND V5FILT 15 18 I with a minimum 1.0 µF, high-quality ceramic capacitor. V5FILT is connected to VREG5 via an internal 10 Ω resistor. Output of 5V linear regulator and supply for MOSFET drivers. Bypass to GND with a VREG5 16 19 O minimum 4.7 µF high-quality ceramic capacitor. VREG5 is connected to V5FILT via an internal 10 Ω resistor. 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS53126 |
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