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DAC1005D650 Datasheet(Hoja de datos) 11 Page - NXP Semiconductors

No. de Pieza. DAC1005D650
Descripción  Dual 10-bit DAC, up to 650 Msps; and interpolating
Descarga  41 Pages
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Fabricante  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
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DAC1005D650_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 28 July 2009
11 of 41
NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2
× 4× and 8× interpolating
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
IO(aux)
auxiliary output current differential outputs
I
-
2.2
-
mA
VO(aux)
auxiliary output voltage compliance range
C
0
-
2
V
NDAC(aux)mono auxiliary DAC
monotonicity
guaranteed
D
-
10
-
bit
Input timing (see Figure 10)
fdata
data rate
Dual-port mode input
C
-
-
160
MHz
tw(CLK)
CLK pulse width
C
1.5
-
Tdata − 1.5 ns
th(i)
input hold time
C
1.1
-
-
ns
tsu(i)
input set-up time
C
1.1
-
-
ns
Output timing
fs
sampling frequency
C
-
-
650
Msps
ts
settling time
to
±0.5 LSB
D
-
20
-
ns
NCO frequency range; fs = 640 Msps
fNCO
NCO frequency
register value = 00000000h
D
-
0
-
MHz
register value = FFFFFFFFh
D
-
640
-
MHz
fstep
step frequency
D
-
0.149 -
Hz
Low-power NCO frequency range; fDAC = 640 MHz
fNCO
NCO frequency
register value = 00000000h
D
-
0
-
MHz
register value = F8000000h
D
-
620
-
MHz
fstep
step frequency
D
-
20
-
MHz
Dynamic performance; PLL on
SFDR
spurious-free dynamic
range
fdata = 80 MHz; fs = 320 Msps;
B=fdata / 2
fo = 35 MHz at 0 dBFS
C
-
82
-
dBc
fdata = 80 MHz; fs = 640 Msps;
B=fdata / 2
fo = 4 MHz at 0 dBFS
I
-
76
-
dBc
fo = 19 MHz at 0 dBFS
I
-
75
-
dBc
fdata = 160 MHz; fs = 640 Msps;
B=fdata / 2
fo = 70 MHz at 0 dBFS
C
-
82
-
dBc
Table 5.
Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb =25 °C; RL =50 Ω;IO(fs) = 20 mA; maximum sample rate; PLL on;
unless otherwise specified.
Symbol
Parameter
Conditions
Test[1]
Min
Typ
Max
Unit




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