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UC2849 Datasheet(PDF) 6 Page - Texas Instruments |
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UC2849 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 11 page 6 CIRCUIT BLOCK DESCRIPTION: PWM Oscillator:The oscillator block diagram with exter- nal connections is shown in Figure 1. A resistor (RT) con- nected to pin RT sets the linear charge current; 2.5V RT . The timing capacitor (CT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4V threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which dis- charges CT. This discharge time with the RC time delay of 2 · CT · RDEAD is the minimum output low time. OSC continues to discharge until it reaches a 1.2V threshold and resets the RS flip-flop which repeats the charging sequence as shown in Figure 2. Equations to approxi- mate frequency and maximum duty cycle are listed under the OSC pin description. Figure 3 and 4 graphs show measured variation of frequency and maximum duty cycle with varying RT, CT, and RDEAD component values. As shown in Figure 5, several oscillators are synchro- nized to the highest free running frequency by connect- ing 100pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately 10k. Referring to Figure1, the synchronization threshold is 1.4V. The oscillator blanks any synchronization pulse that occurs when OSC is below 2.5V. This allows units, once they discharge below 2.5V, to continue through the UC1849 UC2849 UC3849 Figure 2. Oscillator and PWM Output Waveform Figure 1. Oscillator Block with External Connections UDG-94111-1 UDG-94112 VCC: The input voltage of the chip. The chip is opera- tional between 8.4V and 20V. VEE: The negative supply to the chip which powers the lower voltage rail for all amplifiers. The chip is operational if VEE is connected to GND or if GND is floating. When voltage is applied externally to VEE, GND becomes a vir- tual ground because of an internal diode between VEE and GND. The GND current flows through the forward biased diode and out VEE. GND is always the signal ground from which the voltage reference and all amplifier inputs are referenced. VREF: The reference voltage equal to 5.0V. PIN DESCRIPTIONS (cont.) IRT ≈ |
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