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UC1914 Datasheet(PDF) 8 Page - Texas Instruments

No. de pieza UC1914
Descripción Electrónicos  5V to 35V Hot Swap Power Manager
Download  14 Pages
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

UC1914 Datasheet(HTML) 8 Page - Texas Instruments

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UC1914
UC2914
UC3914
shown but can be inferred from the fact that no output
current is provided to the load), latches in the fault and
opens switch S1 disconnecting the charging currents I1
and IPL from CT. Since no output current is supplied, the
load voltage decays at a rate determined by the load
characteristics and the capacitance. The 3
µA current
source, I2, discharges CT to the 0.5V reset comparator
threshold. This time is significantly longer than the charg-
ing time and is the basis for the duty cycle current limiting
technique. When the CT voltage reaches 0.5V at t4, the
part performs a retry, allowing the NMOS to again source
current to the load and cause VOUT to rise. In this partic-
ular example, IMAX is still sourced by the NMOS at each
attempted retry and the fault timing sequence is repeated
until time t7 when the load requirements change to IO.
Since IO is less than the fault current level at this time,
switch S1 is opened, I2 discharges CT and VOUT rises to
almost VCC.
Fig. 3b shows fault timing waveforms similar to those de-
picted in Fig. 3a except that the latch reset (LR) function
is utilized. Operation is the same as described above un-
til t4 when the voltage on CT reaches the reset threshold.
Holding LR high prevents the latch from being reset, pre-
venting the IC from performing a retry (sourcing current
to the load). The UC3914 is latched off until either LR is
pulled to a logic low, or the chip is forced into an under
voltage lockout (UVLO) condition and back out of UVLO
causing the latch to automatically perform a power on re-
set. Fig. 3b illustrates LR being toggled low at t5, causing
the part to perform a retry. Time t6 again illustrates what
happens when a fault is detected. The LR pin is toggled
low and back high at time t7, prior to the voltage on the
CT pin hitting the reset threshold. This information tells
the UC3914 to allow the part to perform a retry when the
lower reset threshold is reached, which occurs at t8.
Time t9 corresponds to when load conditions change to
where a fault is not present as described for Fig. 3a.
Power Limiting
The power limiting circuitry is designed to only source
current into the CT pin. To implement this feature, a re-
sistor, RPL, should be placed between VCC and PLIM.
The current, IPL (show in Fig. 2) is given by the following
expression:
I
VV
R
for V
V
V
PL
CC
OUTS
PL
OUTS
CT
=
>+
,1
where VCT is the voltage on the CT pin. For VOUTS <1V
+VCT the common mode range of the power limiting cir-
cuitry causes IPL = 0 leaving only the 100µA current
source to charge CT.VCC –VOUTS represents the volt-
age across the NMOS pass device.
Later it will be shown how this feature will limit average
power dissipation in the pass device. Note that under a
fault condition where the output current is just above the
fault level, but less than the maximum level, VOUTS ~
VCC, IPL = 0 and the CT charging current is 100µA.
During a fault, the CT pin will charge at a rate deter-
mined by the internal charging current and the external
timing capacitor, CT. Once CT charges to 2.5V, the fault
comparator trips and sets the fault latch. When this oc-
curs, OUT is pulled down to VOUTS, causing the exter-
nal NMOS to shut off and the charging switch, S1, to
open. CT will be discharged with I2 until the CT potential
reaches 0.5V. Once this occurs, the fault latch will reset
(unless LR is being held high, whereby a fault can only
be cleared by pulling this pin low or going through a
power-on-reset cycle), which re-enables the output of the
linear amplifier and allows the fault circuitry to regain
control of the charging switch. If a fault is still present,
the overcurrent comparator will close the charging switch
causing the cycle to repeat. Under a constant fault the
duty cycle is given by:
Duty Cycle
A
IA
PL
=
+
3
100
µ
µ
Average power dissipation can be limited using the PLIM
pin. Average power dissipation in the pass element is
given by:
()
()
PFETavg
VCC
V
I
Duty Cycle
VCC
V
I
OUTS
MAX
OUTS
MAX
=−
=−
3
µA
IA
PL + 100 µ
VCC – VOUTS is the drain to source voltage across the
FET. When IPL >> 100
µA, the duty cycle equation given
above can be rewritten as:
()
Duty Cycle
RPL
A
VCC
VOUTS
=
3
µ
and the average power dissipation of the MOSFET is
given by:
()
()
PFETavg
VCC
VOUTS
IMAX
RPL
A
VCC
VOUTS
IMAX
RPL
=−
=•
3
3
µ
µA
The average power is limited by the programmed IMAX
current and the appropriate value for RPL.
APPLICATION INFORMATION (cont.)


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