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ISL29011 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL29011 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 15 page 7 FN6467.2 May 14, 2009 Register Set There are eight registers that are available in the ISL29011. Table 1 summarizes their functions. Command Register I 00(hex) The first command register has the following functions: 1. Operation Mode: Bits 7, 6, and 5.These three bits determines the operation mode of the device. 2. Interrupt flag; Bit 2. This is the status bit of the interrupt. The bit is set to logic high when the interrupt thresholds have been triggered, and logic low when not yet triggered. Once triggered, INT pin stays low and the status bit stays high. Both interrupt pin and the status bit are automatically cleared at the end of Command Register I transfer. 3. Interrupt persist; Bits 1 and 0. The interrupt pin and the interrupt flag is triggered/set when the data sensor reading is out of the interrupt threshold window after m consecutive number of integration cycles. The interrupt persist bits determine m. FIGURE 2. I2C WRITE TIMING DIAGRAM SAMPLE START W A A A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A A 1 2 615 948 STOP SDA DRIVEN BY MASTER FUNCTIONS REGISTER ADDRESS DEVICE ADDRESS SDA DRIVEN BY MASTER SDA DRIVEN BY MASTER I2C DATA I2C SDA IN I2C SDA OUT I2C CLK IN AA 34 5 7 8 9 2 3 4 6 7 8 1 2 3 5 67 9 A TABLE 1. REGISTER SET ADDR REG NAME BIT 7 6 5 4 3 2 1 0 DEFAULT 00h COMMANDI OP2 OP1 OP0 0 0 FLAG PRST1 PRST0 00h 01h COMMANDII Scheme FREQ IS1 IS0 RES1 RES0 RANGE1 RANGE0 00h 02h DATALSB D7 D6 D5 D4 D3 D2 D1 D0 00h 03h DATAMSB D15 D14 D13 D12 D11 D10 D9 D8 00h 04h INT_LT_LSB TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 00h 05h INT_LT_MSB TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 00h 06h INT_HT_LSB TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 FFh 07h INT_HT_MSB TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 FFh TABLE 2. OPERATION MODE BITS 7 TO 5 OPERATION 000 Power-down the device 001 ALS once 010 IR once 011 Proximity once 100 Reserved (Do not use) 101 ALS continuous 110 IR continuous 111 Proximity continuous TABLE 3. INTERRUPT FLAG BIT 2 OPERATION 0 Interrupt is cleared or not triggered yet 1 Interrupt is triggered TABLE 4. INTERRUPT PERSIST BITS 1 TO 0 NUMBER OF INTEGRATION CYCLES 00 1 01 4 10 8 11 16 ISL29011 |
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