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CS8422-DNZR Datasheet(PDF) 4 Page - Cirrus Logic |
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CS8422-DNZR Datasheet(HTML) 4 Page - Cirrus Logic |
4 / 82 page 4 DS692PP2 CS8422 6.10.2 Software Mode Control ........................................................................................................ 34 7. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 37 7.1 SRC Data Resolution and Dither ................................................................................................... 37 7.1.1 Hardware Mode Control ........................................................................................................ 37 7.1.2 Software Mode Control .......................................................................................................... 37 7.2 SRC Locking .................................................................................................................................. 37 7.3 SRC Muting .................................................................................................................................... 38 7.4 SRC Master Clock ......................................................................................................................... 38 7.4.1 Hardware Mode Control ........................................................................................................ 39 7.4.2 Software Mode Control .......................................................................................................... 39 8. HARDWARE MODE CONTROL .......................................................................................................... 39 8.1 Hardware Mode Serial Audio Port Control ..................................................................................... 40 9. SOFTWARE MODE CONTROL ........................................................................................................... 42 9.1 Control Port Description ................................................................................................................ 42 9.1.1 SPI Mode ............................................................................................................................... 42 9.1.2 I²C Mode ................................................................................................................................ 43 9.1.3 Memory Address Pointer (MAP) ............................................................................................ 43 10. REGISTER QUICK REFERENCE ...................................................................................................... 44 11. SOFTWARE REGISTER BIT DEFINITIONS ...................................................................................... 47 11.1 CS8422 I.D. and Version Register (01h) ..................................................................................... 47 11.2 Clock Control (02h) ...................................................................................................................... 47 11.3 Receiver Input Control (03h) ........................................................................................................ 48 11.4 Receiver Data Control (04h) ........................................................................................................ 48 11.5 GPO Control 1 (05h) .................................................................................................................... 50 11.6 GPO Control 2 (06h) .................................................................................................................... 50 11.7 Serial Audio Input Clock Control (07h) ........................................................................................ 50 11.8 SRC Output Serial Port Clock Control (08h) ...............................................................................51 11.9 Recovered Master Clock Ratio Control & Misc. (09h) ................................................................ 52 11.10 Data Routing Control(0Ah) ......................................................................................................... 52 11.11 Serial Audio Input Data Format (0Bh) ....................................................................................... 53 11.12 Serial Audio Output Data Format - SDOUT1 (0Ch) ................................................................... 54 11.13 Serial Audio Output Data Format - SDOUT2 (0Dh) .................................................................. 55 11.14 Receiver Error Unmasking (0Eh) .............................................................................................. 56 11.15 Interrupt Unmasking (0Fh) ......................................................................................................... 56 11.16 Interrupt Mode (10h) .................................................................................................................. 57 11.17 Receiver Channel Status (11h) ................................................................................................. 57 11.18 Format Detect Status (12h) ........................................................................................................ 58 11.19 Receiver Error (13h) ................................................................................................................. 58 11.20 Interrupt Status (14h) ................................................................................................................ 59 11.21 PLL Status (15h) ....................................................................................................................... 60 11.22 Receiver Status (16h) ............................................................................................................... 61 11.23 Fs/XTI Ratio (17h - 18h) ........................................................................................................... 62 11.24 Q-Channel Subcode (19h - 22h) ................................................................................................ 62 11.25 Channel Status Registers (23h - 2Ch) ....................................................................................... 62 11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h) .......................................................................... 63 12. APPLICATIONS ................................................................................................................................. 64 12.1 Reset, Power Down, and Start-Up ............................................................................................... 64 12.2 Power Supply, Grounding, and PCB layout ................................................................................. 64 12.3 External Receiver Components ................................................................................................... 64 12.3.1 Attenuating Input signals ..................................................................................................... 65 12.3.2 Isolating Transformer Requirements ................................................................................... 66 12.4 Channel Status Buffer Management ............................................................................................ 66 12.4.1 AES3 Channel Status (C) Bit Management ........................................................................ 66 12.4.2 Accessing the E buffer ........................................................................................................ 67 |
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