SMX55161A-75GBI datasheet(11/64 Pages) AUSTIN

No. de pieza	SMX55161A-75GBI

Descripción Electrónicos	262144 x 16 BIT VRAM MULTIPORT VIDEO RAM

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Fabricante Electrónico	AUSTIN [Austin Semiconductor]

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11 / 64 page

VRAM

SM55161A

Production

Austin Semiconductor, Inc.

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

11

SMJ55161A

Rev. 1.6

03/05

FIGURE 4: Example of a Byte-Read Cycle

byte operation

Byte operation can be applied in DRAM-read cycles, write

cycles, block-write cycles, load-write-mask-register cycles, and

load-color-register cycles. In byte operation, the column

address (A0–A8) is latched at the first falling edge of CASx\. In

read cycles, CASL\ enables the lower byte (DQ0–DQ7) and

CASU\ enables the upper byte (DQ8–DQ15) (see Figure 4).

In byte-write operation, CASL enables data to be written

to the lower byte (DQ0–DQ7), and CASU\ enables data to be

written to the upper byte (DQ8–DQ15). In an early write cycle,

WE is brought low prior to both CASx\ signals, and data setup

and hold times for DQ0 –DQ15 are referenced to the first falling

edge of CASx\ (see Figure 5).

For late-write or read-modify-write cycles, WE\ is brought

low after either or both CASL\ and CASU\ fall. The data is

strobed in with data setup and hold times for DQ0 –DQ15

referenced to WE\ (see Figure 6).

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