AD9548BCPZ datasheet(1/112 Pages) AD

No. de pieza	AD9548BCPZ

Descripción Electrónicos	Quad/Octal Input Network Clock Generator/Synchronizer

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Fabricante Electrónico	AD [Analog Devices]

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Quad/Octal Input Network Clock

Generator/Synchronizer

AD9548

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Supports Stratum 2 stability in holdover mode

Supports reference switchover with phase build-out

Supports hitless reference switchover

Auto/manual holdover and reference switchover

4 pairs of reference input pins with each pair configurable as

a single differential input or as 2 independent single-

ended inputs

Input reference frequencies from 1 Hz to 750 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

30-bit programmable input reference divider

4 pairs of clock output pins with each pair configurable as a

single differential LVDS/LVPECL output or as 2 single-

ended CMOS outputs

Output frequencies up to 450 MHz

30-bit integer and 10-bit fractional programmable feedback

divider

Programmable digital loop filter covering loop bandwidths

from 0.001 Hz to 100 kHz

Optional low noise LC-VCO system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Software controlled power-down

88-lead LFCSP package

APPLICATIONS

Network synchronization

Cleanup of reference clock jitter

GPS 1 pulse per second synchronization

SONET/SDH clocks up to OC-192, including FEC

Stratum 2 holdover, jitter cleanup, and phase transient

control

Stratum 3E and Stratum 3 reference clocks

Wireless base station controllers

Cable infrastructure

Data communications

GENERAL DESCRIPTION

The AD9548 provides synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9548 generates an output clock synchronized to one of up to

four differential or eight single-ended external input references.

The digital PLL allows for reduction of input time jitter or phase

noise associated with the external references. The AD9548

continuously generates a clean (low jitter), valid output clock

even when all references have failed by means of a digitally

controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFERENCE INPUTS

AND

MONITOR MUX

STATUS AND

CONTROL PINS

SERIAL CONTROL INTERFACE

(SPI or I2C)

EEPROM

DIGITAL

PLL

CLOCK DISTRIBUTION

SYNC

DAC

CLOCK

MULTIPLIER

STABLE

SOURCE

ANALOG

FILTER

AD9548

CHANNEL 0

DIVIDER

CHANNEL 1

DIVIDER

CHANNEL 2

DIVIDER

CHANNEL 3

DIVIDER

Figure 1.

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