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ADCLK954 Datasheet(PDF) 1 Page - Analog Devices

No. de pieza ADCLK954
Descripción Electrónicos  Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADCLK954 Datasheet(HTML) 1 Page - Analog Devices

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Two Selectable Inputs, 12 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK954
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalog Devices foritsuse,nor for anyinfringements ofpatents orother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
FEATURES
FEATURES
2 selectable differential inputs
2 selectable differential inputs
4.8 GHz operating frequency
4.8 GHz operating frequency
75 fs rms broadband random jitter
75 fs rms broadband random jitter
On-chip input terminations
On-chip input terminations
3.3 V power supply
3.3 V power supply
APPLICATIONS
APPLICATIONS
Low jitter clock distribution
Low jitter clock distribution
Clock and data signal restoration
Clock and data signal restoration
Level translation
Level translation
Wireless communications
Wireless communications
Wired communications
Wired communications
Medical and industrial imaging
Medical and industrial imaging
ATE and high performance instrumentation
ATE and high performance instrumentation
GENERAL DESCRIPTION
GENERAL DESCRIPTION
The ADCLK954 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The ADCLK954 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK954 features 12 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ADCLK954 features 12 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC − 2 V for a total differential
output swing of 1.6 V.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC − 2 V for a total differential
output swing of 1.6 V.
The ADCLK954 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
The ADCLK954 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
VT0
VREF0
VREF1
IN_SEL
CLK0
CLK0
VT1
CLK1
CLK1
LVPECL
ADCLK954
REFERENCE
REFERENCE
Figure 1.


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