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ADIS16405 Datasheet(PDF) 6 Page - Analog Devices |
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ADIS16405 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 20 page  ADIS16400/ADIS16405 Rev. B | Page 6 of 20 TIMING SPECIFICATIONS TA = 25°C, VCC = 5 V, unless otherwise noted. Table 2. Normal Mode (SMPL_PRD ≤ 0x09) Low Power Mode (SMPL_PRD ≥ 0x0A) Burst Mode Parameter Description Min1 Typ Max Min1 Typ Max Min1 Typ Max Unit fSCLK Serial clock frequency 0.01 2.0 0.01 0.3 0.01 1.0 MHz tSTALL Stall period between data 9 75 1/fSCLK μs tREADRATE Read rate 40 150 μs tCS Chip select to clock edge 48.8 48.8 48.8 ns tDAV DOUT valid after SCLK edge 100 100 100 ns tDSU DIN setup time before SCLK rising edge 24.4 24.4 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 48.8 48.8 ns tSCLKR, tSCLKF SCLK rise/fall times 5 12.5 5 12.5 5 12.5 ns tDF, tDR DOUT rise/fall times 5 12.5 5 12.5 5 12.5 ns tSFS CS high after SCLK edge 5 5 5 ns t1 Input sync pulse width 5 5 μs t2 Input sync to data ready output 600 600 μs t3 Input sync period 833 833 μs DIN 1Guaranteed by design and characterization but not tested in production. TIMING DIAGRAMS CS SCLK DOUT 1 2 3 4 5 6 15 16 W/R A5 A6 A4 A3 A2 D2 MSB DB14 D1 LSB DB13 DB12 DB10 DB11 DB2 LSB DB1 tCS tSFS tDAV tDHD tDSU Figure 2. SPI Timing and Sequence CS SCLK tREADRATE tSTALL Figure 3. Stall Time and Data Rate t3 t2 t1 SYNC CLOCK (DIO4) DATA READY Figure 4. Input Clock Timing Diagram |
Número de pieza similar - ADIS16405 |
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Descripción similar - ADIS16405 |
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