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ADIS16400BMLZ Datasheet(PDF) 10 Page - Analog Devices |
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ADIS16400BMLZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page ADIS16400/ADIS16405 Rev. B | Page 10 of 20 THEORY OF OPERATION BASIC OPERATION The ADIS16400/ADIS16405 are autonomous sensor systems that start up after a valid power supply voltage is applied and then begin producing inertial measurement data at the factory- default sample rate of 819.2 SPS. After each sample cycle, the sensor data loads into the output registers and DIO1 pulses, providing a new data ready control signal for driving system- level interrupt service routines. In a typical system, a master processor accesses the output data registers through the SPI interface, using the hook-up shown in Figure 9. Table 6 provides a generic functional description for each pin on the master processor. Table 7 describes the typical master processor settings normally found in a configuration register and used for communicating with the ADIS16400/ADIS16405. SYSTEM PROCESSOR SPI MASTER ADIS16405 SPI SLAVE SCLK CS DIN DOUT SCLK SS MOSI MISO 5V IRQ DIO1 VDD I/O LINES ARE COMPATIBLE WITH 3.3V OR 5V LOGIC LEVELS 10 6 3 5 4 7 11 12 13 14 15 Figure 9. Electrical Hook-Up Diagram Table 6. Generic Master Processor Pin Names and Functions Pin Name Function SS Slave select IRQ Interrupt request MOSI Master output, slave input MISO Master input, slave output SCLK Serial clock Table 7. Generic Master Processor SPI Settings Processor Setting Description Master The ADIS16400/ADIS16405 operate as a slave. SCLK Rate ≤ 2 MHz1 Normal mode, SMPL_PRD[7:0] ≤ 0x08. CPOL = 1 Clock polarity. CPHA = 1 Clock phase. MSB-First Bit sequence. 16-Bit Shift register/data length. 1 For burst mode, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz. The user registers provide addressing for all input/output operations on the SPI interface. Each 16-bit register has two 7-bit addresses: one for its upper byte and one for its lower byte. Table 8 lists the lower byte address for each register, and Figure 10 shows the generic bit assignments. UPPER BYTE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOWER BYTE Figure 10. Output Register Bit Assignments READING SENSOR DATA Although the ADIS16400/ADIS16405 produce data indepen- dently, these operate as SPI slave devices that communicate with system (master) processors using the 16-bit segments displayed in Figure 11. Individual register reads require two such 16-bit sequences. The first 16-bit sequence provides the read command bit (R/W = 0) and the target register address (A6 to A0). The second sequence transmits the register contents (D15 to D0) on the DOUT line. For example, if DIN = 0x0A00, the content of XACCL_OUT shifts out on the DOUT line during the next 16-bit sequence. The SPI operates in full duplex mode, which means that the master processor can read the output data from DOUT while using the same SCLK pulses to transmit the next target address on DIN. DEVICE CONFIGURATION The user register memory map (Table 8) identifies configuration registers with either a W (write only) or R/W (read/write). Configuration commands also use the bit sequence displayed in Figure 11. If the MSB is equal to 1, the last eight bits (DC7 to DC0) in the DIN sequence load into the memory address associated with the address bits (A5 to A0). For example, if DIN = 0xA11F, then 0x1F loads into Address Location 0x21 (XACCL_OFF, upper byte) at the conclusion of the data frame. Most of the registers have a backup location in nonvolatile flash memory. The master processor must manage the backup function. Set GLOB_CMD[3] = 1 (DIN = 0xBE04) to execute a manual flash update (backup) operation, which copies the user registers into their respective flash memory locations. This operation takes 50 ms and requires the power supply voltage to be within the specified limit to complete properly. The FLASH_CNT register provides a running count of these events for managing the long- term reliability of the flash memory. BURST MODE DATA COLLECTION Burst mode data collection offers a more efficient method for collecting data from the ADIS16400/ADIS16405. In sequential data cycles (each separated by one SCLK period), all output registers clock out on DOUT. This sequence starts when the DIN sequence is 0011 1110 0000 0000 (0x3E00). Next, the contents of each output register are output from DOUT, starting with SUPPLY_OUT and ending with AUX_ADC (see Figure 12). The addressing sequence shown in Table 8 determines the order of the outputs in burst mode. |
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