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www.fairchildsemi.com

FAN3268 • Rev. 1.0.0

2

Ordering Information

Part Number

Logic

Input Threshold

Eco Status

Packing Method

FAN3268TMX

Non-Inverting Channel and

Inverting Channel + Dual Enables

TTL

RoHS

2,500 Units on

Tape & Reel

Package Outline

Figure 2. Pin Configuration (Top View)

Thermal Characteristics

(1)

Package

Θ

JL

(2)

Θ

JT

(3)

Θ

JA

(4)

Ψ

JB

(5)

Ψ

JT

(6)

Units

8-Pin Small Outline Integrated Circuit (SOIC)

40

31

89

43

3

°C/W

Notes:

1.

Estimates derived from thermal simulation; actual values depend on the application.

2.

Theta_JL (

thermal pad) that are typically soldered to a PCB.

3.

Theta_JT (

held at a uniform temperature by a top-side heatsink.

4.

The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and

JESD51-7, as appropriate.

5.

Psi_JB (

application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board

reference is defined as the PCB copper adjacent to pin 6.

6.

Psi_JT (

the center of the top of the package for the thermal environment defined in Note 4.