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FDZ371PZ Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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FDZ371PZ Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 7 page  www.fairchildsemi.com 2 ©2009 Fairchild Semiconductor Corporation FDZ371PZ Rev.C Electrical Characteristics T J = 25 °C unless otherwise noted Off Characteristics On Characteristics Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics Symbol Parameter Test Conditions Min Typ Max Units BVDSS Drain to Source Breakdown Voltage ID = -250 µA, VGS = 0 V -20 V ∆BV DSS ∆T J Breakdown Voltage Temperature Coefficient ID = -250 µA, referenced to 25 °C 22 mV/°C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V -1 µA IGSS Gate to Source Leakage Current VGS = ±8 V, VDS = 0 V ±10 µA VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = -250 µA-0.35 -0.6 -1.0 V ∆V GS(th) ∆T J Gate to Source Threshold Voltage Temperature Coefficient ID = -250 µA, referenced to 25 °C -4 mV/°C rDS(on) Static Drain to Source On Resistance VGS = -4.5 V, ID = -2.0 A 55 75 m Ω VGS = -2.5 V, ID = -1.5A 65 90 VGS = -1.8 V, ID = -1.0 A 80 110 VGS = -1.5 V, ID = -1.0 A 100 150 VGS = -4.5 V, ID = -2.0 A, TJ =125°C 80 124 gFS Forward Transconductance VDD = -5 V, ID = -3.3 A 14 S Ciss Input Capacitance VDS = -10 V, VGS = 0 V, f = 1 MHz 750 1000 pF Coss Output Capacitance 110 145 pF Crss Reverse Transfer Capacitance 100 150 pF td(on) Turn-On Delay Time VDD = -10 V, ID = -3.3 A, VGS = -4.5 V, RGEN = 6 Ω 5.9 12 ns tr Rise Time 9.1 18 ns td(off) Turn-Off Delay Time 124 198 ns tf Fall Time 88 140 ns Qg Total Gate Charge VGS = -4.5 V, VDD = -10 V, ID = -3.3 A 12 17 nC Qgs Gate to Source Charge 1.1 nC Qgd Gate to Drain “Miller” Charge 3.4 nC IS Maximum Continuous Drain-Source Diode Forward Current -1.1 A VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -0.7 -1.2 V trr Reverse Recovery Time IF = -3.3 A, di/dt = 100 A/µs 61 98 ns Qrr Reverse Recovery Charge 29 47 nC Notes: 1. RθJA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection ESD. No gate overvoltage rating is implied. a. 75 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 260 °C/W when mounted on a minimum pad of 2 oz copper. |
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