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ADG1439BCPZ-REEL7 Datasheet(PDF) 9 Page - Analog Devices |
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ADG1439BCPZ-REEL7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page ADG1438/ADG1439 Rev. 0 | Page 9 of 20 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 3). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.1 Table 7. Parameter Limit at TMIN, TMAX Unit Conditions/Comments t12 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 5 ns min SYNC to SCLK active edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 5 ns min SCLK active edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 5 ns min SYNC rising edge to next SCLK active edge ignored t10 5 ns min SCLK active edge to SYNC falling edge ignored t113 40 ns max SCLK rising edge to SDO valid t12 15 ns min Minimum RESET pulse width 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 3 Measured with the 1 k Ω pull-up resistor to V L and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode. TIMING DIAGRAM t4 t3 SCLK SYNC DIN t1 t2 t5 t6 t7 t8 DB7 t9 t10 t12 DB0 RESET Figure 3. Serial Write Operation t8 t4 t3 t6 t11 t7 t9 t5 816 SCLK SYNC DIN SDO UNDEFINED INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N + 1 t1 t2 DB0 DB7 DB0 DB7 DB7 DB0 Figure 4. Daisy-Chain Timing Diagram |
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