Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼

Delete All
ON OFF
ALLDATASHEET.ES

X  

Preview PDF Download HTML

ATmega16U2 Datasheet(PDF) 13 Page - ATMEL Corporation

No. de pieza ATmega16U2
Descripción Electrónicos  8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller
Download  314 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATmega16U2 Datasheet(HTML) 13 Page - ATMEL Corporation

Back Button ATmega16U2 Datasheet HTML 9Page - ATMEL Corporation ATmega16U2 Datasheet HTML 10Page - ATMEL Corporation ATmega16U2 Datasheet HTML 11Page - ATMEL Corporation ATmega16U2 Datasheet HTML 12Page - ATMEL Corporation ATmega16U2 Datasheet HTML 13Page - ATMEL Corporation ATmega16U2 Datasheet HTML 14Page - ATMEL Corporation ATmega16U2 Datasheet HTML 15Page - ATMEL Corporation ATmega16U2 Datasheet HTML 16Page - ATMEL Corporation ATmega16U2 Datasheet HTML 17Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 314 page
background image
13
7799B–AVR–07/09
ATmega8U2/16U2/32U2
6.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 246 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 64. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 64 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Memory Programming” on page 246.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn