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AD5541ABCPZ-1 Datasheet(PDF) 13 Page - Analog Devices |
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AD5541ABCPZ-1 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 24 page  Preliminary Technical Data AD5541A/AD5542A/AD5512AA Rev. P rA | Page 13 of 24 THEORY OF OPERATION The AD5541A/AD5542A/AD5512A are single, 16-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5 V and consume typically 300 µA with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts are designed with a power-on reset function. In unipolar mode, the output is reset to 0 V; in bipolar mode, the AD5542 output is set to −VREF. Kelvin sense connections for the reference and analog ground are included on the AD5542. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 30. The DAC architecture of the AD5541/AD5542 is segmented. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data-word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network. 2R . . . . . S1 . . . . . 2R S11 2R E1 2R . . . . . E2 . . . . . 2R 2R S0 2R E15 R R VREF VOUT 12-BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS Figure 30. DAC Architecture With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: N REF OUT D V V 2 × = where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following: 536 , 65 5 . 2 D V OUT × = This gives a VOUT of 1.25 V with midscale loaded, and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/65,536. SERIAL INTERFACE The AD5541/AD5542 are controlled by a versatile 3- or 4-wire serial interface that operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 5. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 16-bit words. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can be loaded to the part only while CS is low. The AD5542 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC can be tied perma- nently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS loads the data to the DAC. UNIPOLAR OUTPUT OPERATION These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low supply current, typically 300 μA, and a low offset error. The AD5541 provides a unipolar output swing ranging from 0 V to VREF. The AD5542 can be configured to output both unipolar and bipolar voltages. Figure 31 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 6. OUT REFS* REF(REFF*) DGND AGND VDD DIN SCLK LDAC* CS AD5541/AD5542 AD820/ OP196 0.1µF 0.1µF 10µF UNIPOLAR OUTPUT EXTERNAL OP AMP 2.5V 5V SERIAL INTERFACE *AD5542 ONLY. Figure 31. Unipolar Output Table 6. Unipolar Code Table DAC Latch Contents MSB LSB Analog Output 1111 1111 1111 1111 VREF × (65,535/65,536) 1000 0000 0000 0000 VREF × (32,768/65,536) = ½ VREF 0000 0000 0000 0001 VREF × (1/65,536) 0000 0000 0000 0000 0 V |
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