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ES5117Q Datasheet(PDF) 7 Page - Cyrustek corporation |
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ES5117Q Datasheet(HTML) 7 Page - Cyrustek corporation |
7 / 10 page 03/07/21 7 ES5117 3 1/2 DVM with LED Display and Hold reference integrate cycle is stored on C REF. A 0.1uF value capacitor is acceptable when INLO is connected with COMMON. A mylar type dielectric capacitor is adequate. 8. TEST The TEST pin is tied to the negative logic supply through a 500 Ω resistor. When TEST is pulled high to V+ all segments will be turned on and the display should read -1888. 9. Hold When the hold pin is connected to V+ the conversion result will not be update. The conversion is still free running during hold mode. TEST Circuit 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 100p 100K 0.1u 1M 1K 24K +IN- +5V LED Display Clock Frequency 48KHz (3 readings/second) -5V 0V |
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Descripción similar - ES5117Q |
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