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BD9130EFJ Datasheet(PDF) 8 Page - Rohm

No. de Pieza. BD9130EFJ
Descripción  Output 2A or More High-efficiency Step-down Switching Regulator with Built-in Power MOSFET
Descarga  15 Pages
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Fabricante  ROHM [Rohm]
Página de inicio  http://www.rohm.com
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BD9130EFJ Datasheet(HTML) 8 Page - Rohm

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BD9130EFJ
Technical Note
8/14
www.rohm.com
2009.05 - Rev.A
© 2009 ROHM Co., Ltd. All rights reserved.
IC only
θj-a=249.5℃/W
1 layers(copper foil area:0mm×0mm)
θj-a=153.2℃/W
2 layers(copper foil area:15mm×15mm)
θj-a=113.6℃/W
2 layers(copper foil area:70mm×70mm)
θj-a=59.2℃/W
4 layers(copper foil area:70mm×70mm)
θj-a=33.3℃/W
(when mounted on a board 70mm×70mm×1.6mm
Glass-epoxy PCB with termal Via)
Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET:PD(I
2R)
2) Gate charge/discharge dissipation:PD(Gate)
3) Switching dissipation:PD(SW)
4) ESR dissipation of capacitor:PD(ESR)
5) Operating current dissipation of IC:PD(IC)
1)PD(I
2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]:DC resistance of inductor, RON[Ω]:ON resistance of FET, IOUT[A]:Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET、f[H]:Switching frequency、V[V]:Gate driving voltage of FET)
4)PD(ESR)=IRMS
2×ESR (IRMS[A]:Ripple current of capacitor、ESR[Ω]:Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]:Circuit current.)
Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
Fig.26 Thermal derating curve
(HTSOP-J8)
If VCC=3.3V, VOUT=1.8V, RONP=0.2Ω, RONN=0.16Ω
IOUT=2A, for example,
D=VOUT/VCC=1.8/3.3=0.545
RON=0.545×0.20+(1-0.545)×0.16
=0.109+0.0728
=0.1818[Ω]
P=2
2×0.1818=0.7272W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
η= VOUT×IOUT
Vin×Iin
×100[%]= POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Vin
2×CRSS×IOUT×f
IDRIVE
3)PD(SW)=
(CRSS[F]:Reverse transfer capacitance of FET、IDRIVE[A]:Peak current of gate.)
P=IOUT
2×RON
RON=D×RONP+(1-D)RONN
D:ON duty (=VOUT/VCC)
RCOIL:DC resistance of coil
RONP:ON resistance of P-channel MOS FET
RONN:ON resistance of N-channel MOS FET
IOUT:Output current
Ambient temperature:Ta [℃]
0
25
50
75
100
125
150
0
2.0
3.0
4.0
0.50W
105
1.0
0.50W
0.82W
1.10W
2.11W
3.76W


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