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SS6550COTB Datasheet(PDF) 8 Page - Silicon Standard Corp. |
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SS6550COTB Datasheet(HTML) 8 Page - Silicon Standard Corp. |
8 / 13 page www.SiliconStandard.com 8 of 13 SS6550 n BLOCK DIAGRAM 10 Q3 5 VIN REF FB REF REF GND LX SHDN BP C hip Supply C ontrol Logic Selection Frequency SYNC RT O scillator 500KHz + - C ompensation S lope C urrent Limit C omparator C urrent AMP . + - X 5 0.75V REF Zero C ross C omparator C omparator A nti- Shoot- Through + - + - VIN Control PWM/PFM PFM + - C omparator PWM AMP . Error + - P hase Compensation FB Q1 x1 Q1 X20 n PIN DESCRIPTIONS PIN 1: VIN- Supply voltage input. Input range from +2.5V to +5.5V. Bypass with a 10µF capacitor. PIN 2: BP- Supply bypass pin, internally con- nected to VIN. Bypass with a 0.1µF capacitor. Do not connect to an ex- ternal power source other than VIN. PIN 3: SHDN - Active-low, shutdown-control input. Reduces supply current to 0.1µA in shutdown. PIN 4: FB- Feedback input. PIN 5: RT- Frequency adjustable pin. Connect a resistor from this pin to GND to de- crease the frequency. PIN 6: SYNC/MODE- Oscillator sync and low-noise, mode-control Input. SYNC/MODE = VIN (Forced PWM mode) SYNC/MODE = GND (PWM/PFM mode) An external clock signal connected to this pin allows for LX switching synchronization. PIN 7: GND- Ground. PIN 8: LX- Inductor connection to the drains of the internal power MOSFETs Rev.2.01 6/06/2003 |
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