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AD9553BCPZ Datasheet(PDF) 10 Page - Analog Devices |
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AD9553BCPZ Datasheet(HTML) 10 Page - Analog Devices |
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10 / 44 page  AD9553 Rev. 0 | Page 10 of 44 NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 Y4 2 Y5 3 A0 4 A1 5 A2 6 A3 7 REFA 8 REFB/REFA 24 GND 23 OUT2 22 21 VDD 20 LOCKED 19 LDO 18 VDD 17 LDO TOP VIEW (Not to Scale) AD9553 OUT2 Figure 2. Pin Configuration Table 13. Pin Function Descriptions Pin No. Mnemonic Type1 Description 29, 30, 31, 32, 1, 2 Y0, Y1, Y2, Y3, Y4, Y5 I Control Pins. These pins select one of 51 preset output frequency combinations for OUT1 and OUT2. Note that when all six control pins are Logic 0, SPI programming is active. 3, 4, 5, 6 A0, A1, A2, A3 I Control Pins. These pins select one of 15 preset input reference frequencies. Note that when all four control pins are Logic 0, SPI programming is active. 7 REFA I Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively, this pin is the noninverted part of a differential clock input signal. 8 REFB/REFA I Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively, this pin is the inverted part of a differential clock input signal. 9, 10 XTAL I Crystal Resonator Input. Connect a crystal resonator across these pins. When using the preset input/output frequencies via the Y[5:0] and A[3:0] pins, the crystal must have a resonant frequency of 25 MHz with a specified load capacitance of 10 pF. 11 SEL REFB I Control Pin. This pin allows manual selection of REFA (Logic 0) or REFB (Logic 1) as the active reference assuming that the desired reference signal is present. Note that this pin is nonfunctional when Register 0x29[5] = 1. 12 OM2/CS I Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM2) with an internal 40 kΩ pull-up resistor. The OM2 pin, in conjunction with the OM0 and OM1 pins, allows the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is an active low chip select (CS) with no internal pull-up resistor. 13 OM1/SCLK I Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM1) with an internal 40 kΩ pull-up resistor. The OM1 pin, in conjunction with the OM0 and OM2 pins, allows the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is the serial data clock (SCLK) with no internal pull-up resistor. 14 OM0/SDIO I/O Digital Input/Output. When the device is not in SPI mode, this pin is an input only and functions as an output mode control pin (OM0) with an internal 40 kΩ pull-up resistor. The OM0 pin, in conjunction with the OM1 and OM2 pins, allows the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is the serial data input/output (SDIO) with no internal pull-up resistor. 15 RESET I Digital Input, Active Low with a 100 kΩ Internal Pull-Up Resistor. Resets the internal logic to default states (see the Automatic Power-On Reset section). 16 FILTER I/O Loop Filter Node for the PLL. Connect external loop filter components (see Figure 22) from this pin to Pin 17 (LDO). 17, 19 LDO P/O LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground. 18, 21, 28 VDD P Power Supply Connection: 3.3 V Analog Supply. 20 LOCKED O Active High Locked Status Indicator for the PLL. 26, 22 OUT1, OUT2 O Complementary Square Wave Clocking Outputs. 27, 23 OUT1, OUT2 O Square Wave Clocking Outputs. 24, 25 GND P Ground. EP Exposed die pad The exposed die pad must be connected to GND. 1 I = input, I/O = input/output, O = output, P = power, and P/O = power/output. |
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