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74AUP1G80 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G80 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 18 page 74AUP1G80_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 20 October 2006 3 of 18 NXP Semiconductors 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 80 DVCC CP GND Q 001aac563 1 2 3 5 4 74AUP1G80 74AUP1G80 CP 001aac522 D GND n.c. VCC Q Transparent top view 2 3 1 5 4 6 74AUP1G80 CP 001aaf507 D GND n.c. VCC Q Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description TSSOP5 XSON6 D 1 1 data input D CP 2 2 clock pulse input CP GND 3 3 ground (0 V) Q 4 4 data output Q n.c. - 5 not connected VCC 5 6 supply voltage Table 4. Function table[1] Input Output CP D Q ↑ LH ↑ HL LX q |
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